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wireless charger a/d flash mcu HT66FW2230 revision: v1.20 date: january 3, 2017
rev. 1.20 2 january 3, 2017 rev. 1.20 3 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu table of contents eates cpu features ......................................................................................................................... 7 peripheral features ................................................................................................................. 7 general description ......................................................................................... 8 block diagram .................................................................................................. 8 pin assignment ........... ..................................................................................... 9 pin descriptions .............................................................................................. 9 absolute maximum ratings ........................................................................... 11 d.c. characteristics ....................................................................................... 12 a.c. characteristics ....................................................................................... 13 a/d characteristics ........................................................................................ 13 pll electrical characteristics ... ................................................................... 14 ocp electrical characteristics ..................................................................... 14 reference voltage electrical characteristics .............................................. 15 power on reset electrical characteristics .................................................. 15 system architecture ...................................................................................... 16 clocking and pipelining ......................................................................................................... 16 program counter ................................................................................................................... 17 stack ..................................................................................................................................... 17 arithmetic and logic unit C alu ........................................................................................... 18 flash program memory ................................................................................. 18 structure ................................................................................................................................ 18 special vectors ..................................................................................................................... 18 look-up table ............. ........................................................................................................... 19 table program example ........................................................................................................ 20 in circuit programming C icp ............................................................................................... 21 on-chip debug support C ocds ......................................................................................... 22 ram data memory ......................................................................................... 22 structure ................................................................................................................................ 22 special function register description ........................................................ 24 indirect addressing registers C iar0, iar1, iar2 ............................................................... 24 memory pointers C mp0, mp1l, mp1h, mp2l, mp2h ......................................................... 24 accumulator C acc ............................................................................................................... 25 program counter low register C pcl .................................................................................. 25 look-up table registers C tblp, tbhp, tblh ..................................................................... 25 status register C status .................................................................................................... 25
rev. 1.20 2 january 3, 2017 rev. 1.20 3 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu eeprom data memory ........... ....................................................................... 27 eeprom data memory structure ........................................................................................ 27 eeprom registers ............ .................................................................................................. 27 reading data from the eeprom ........................................................................................ 29 writing data to the eeprom ................................................................................................ 29 write protection ..................................................................................................................... 29 eeprom interrupt ............. ................................................................................................... 29 programming considerations ............. ................................................................................... 30 oscillator ........................................................................................................ 31 oscillator overview ............. .................................................................................................. 31 system clock confgurations ................................................................................................ 31 external crystal/ ceramic oscillator C hxt .......................................................................... 32 internal rc oscillator C hirc ............. .................................................................................. 32 internal 32khz oscillator C lirc ........................................................................................... 32 operating modes and system clocks ......................................................... 33 system clocks ...................................................................................................................... 33 system operation modes ...................................................................................................... 34 control register .................................................................................................................... 35 operating mode switching .................................................................................................... 36 normal mode to slow mode switching ........................................................................... 37 slow mode to normal mode switching ........................................................................... 37 entering the sleep mode .................................................................................................... 39 entering the idle0 mode ...................................................................................................... 39 entering the idle1 mode ...................................................................................................... 39 entering the idle2 mode ...................................................................................................... 40 standby current considerations ........................................................................................... 40 wake-up ................................................................................................................................ 41 programming considerations ............. ................................................................................... 41 watchdog timer ........... .................................................................................. 42 watchdog timer clock source .............................................................................................. 42 watchdog timer control register ............. ............................................................................ 42 watchdog timer operation ................................................................................................... 43 reset and initialisation .................................................................................. 44 reset overview ..................................................................................................................... 44 reset functions ............. ....................................................................................................... 45 reset initial conditions ......................................................................................................... 48 input/output ports ......................................................................................... 51 pull-high resistors ................................................................................................................ 51 port a wake-up ............. ........................................................................................................ 52 i/o port control registers ..................................................................................................... 52 i/o pin structures .................................................................................................................. 53 pin-sharing functions ........................................................................................................... 54 programming considerations ............. ................................................................................... 57
rev. 1.20 4 january 3, 2017 rev. 1.20 5 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu timer modules C tm .......... ............................................................................ 58 introduction ........................................................................................................................... 58 tm operation ............. ........................................................................................................... 58 tm clock source ............. ...................................................................................................... 58 tm interrupts ......................................................................................................................... 59 tm external pins ................................................................................................................... 59 tm input/output pin control register ................................................................................... 59 programming considerations ............. ................................................................................... 60 compact type tm C ctm .............................................................................. 61 compact tm operation ......................................................................................................... 61 compact type tm register description ................................................................................ 62 compact type tm operating modes .................................................................................... 66 compare match output mode ............................................................................................... 66 timer/counter mode ............................................................................................................. 69 pwm output mode ............. ................................................................................................... 69 standard type tm C stm .......... .................................................................... 72 standard tm operation ............. ............................................................................................ 72 standard type tm register description ............................................................................... 73 standard type tm operating modes .................................................................................... 76 compare output mode ............. ............................................................................................. 76 timer/counter mode ............................................................................................................. 79 pwm output mode ............. ................................................................................................... 79 single pulse mode ................................................................................................................ 81 capture input mode .............................................................................................................. 83 analog to digital converter .......... ................................................................ 84 a/d overview ............. ........................................................................................................... 84 a/d converter register description ...................................................................................... 84 a/d converter data registers C adrl, adrh ..................................................................... 85 a/d converter control registers C adcr0, adcr1 ............................................................. 85 a/d operation ....................................................................................................................... 87 a/d input pins ............. .......................................................................................................... 88 summary of a/d conversion steps ............. .......................................................................... 89 programming considerations ............. ................................................................................... 90 a/d transfer function ............. .............................................................................................. 90 a/d programming examples ................................................................................................. 91
rev. 1.20 4 january 3, 2017 rev. 1.20 5 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu i 2 c interface ................................................................................................... 93 i 2 c interface operation ......................................................................................................... 93 i 2 c registers ......................................................................................................................... 94 i 2 c bus communication ....................................................................................................... 97 i 2 c bus start signal .............................................................................................................. 98 slave address ...................................................................................................................... 98 i 2 c bus read/write signal ................................................................................................... 99 i 2 c bus slave address acknowledge signal ........................................................................ 99 i 2 c bus data and acknowledge signal ............ .................................................................... 99 i 2 c time-out control ............................................................................................................ 101 pll clock generator .................................................................................. 102 clock generator operation ................................................................................................. 102 clock generator register description ............. .................................................................... 103 pwm output control ............................................................................................................. 105 demodulation function ........... .................................................................... 107 demodulat or circuit operation ............. ............................................................................... 107 input voltage range ............................................................................................................ 108 offset calibration ................................................................................................................ 108 demodulat or register description ...................................................................................... 109 ocp function ................................................................................................ 112 ocp circuit operation ......................................................................................................... 112 input voltage range ............................................................................................................. 112 offset calibration ................................................................................................................. 113 ocp register description ............. ....................................................................................... 113 internal reference voltage C ivref ............................................................ 116 demodulat or & ocp miscellaneous control register description ....................................... 116 interrupts ....................................................................................................... 117 interrupt registers ................................................................................................................ 117 interrupt operation .............................................................................................................. 121 external interrupt ............. .................................................................................................... 122 multi-function interrupt ........................................................................................................ 123 ocp interrupt ...................................................................................................................... 123 demodulation interrupt ........................................................................................................ 123 a/d converter interrupt ....................................................................................................... 123 time base interrupts ........................................................................................................... 124 eeprom interrupt ............. ................................................................................................. 125 lvd interrupt ....................................................................................................................... 125 tm interrupts ....................................................................................................................... 126 i 2 c interrupt ............. ............................................................................................................ 126 interrupt wake-up function ................................................................................................. 126 programming considerations ............. ................................................................................. 127
rev. 1.20 6 january 3, 2017 rev. 1.20 7 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu low voltage detector C lvd .......... ............................................................. 128 lvd register ............. .......................................................................................................... 128 lvd operation ..................................................................................................................... 129 application circuits ........... .......................................................................... 130 wpc type a11 transmitter ................................................................................................. 130 bill of materials .................................................................................................................... 132 instruction set .............................................................................................. 133 introduction ......................................................................................................................... 133 instruction timing ................................................................................................................ 133 moving and transferring data ............................................................................................. 133 arithmetic operations .......................................................................................................... 133 logical and rotate operation ............................................................................................. 134 branches and control transfer ........................................................................................... 134 bit operations ..................................................................................................................... 134 table read operations ....................................................................................................... 134 other operations ............. .................................................................................................... 134 instruction set summary .......... .................................................................. 135 table conventions ............................................................................................................... 135 instruction defnition ................................................................................... 137 package information ................................................................................... 146 28-pin ssop (150mil) outline dimensions ......................................................................... 147
rev. 1.20 6 january 3, 2017 rev. 1.20 7 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu features cpu features ? operating v oltage : f sys = 20mhz: 4.0v~5.5v ? up to 0.2s instruction cycle with 20mhz system clock at v dd =5v ? power down and wake-up functions to reduce power consumption ? oscillators external crystal oscillator C hxt internal 20mhz rc oscillator C hirc internal 32khz C lirc ? multi-mode operation: normal, slow, idle and sleep ? all instructions executed in one or two instruction cycles ? table read instructions ? 63 powerful instructions ? 8-level subroutine nesting ? bit manipulation instruction peripheral features ? flash program memory: 4k16 ? ram data memory: 1288 ? true eeprom memory: 648 ? watchdog t imer function ? up to 17 bidirectional i/o lines ? two pin-shared external interrupts ? multiple t imer module for time measure, input capture, compare match output, pwm output function or single pulse output function ? i 2 c function ? over current protection (ocp) and demodulation functions ? clock generator output: 100khz~220khz in 100hz steps 1mhz ? 2.08v reference voltage for adc ? dual t ime-base functions for generation of fxed time interrupt signals ? multi-channel 12-bit resolution a/d converter ? low voltage reset function ? low voltage detect function ? package: 28-pin ssop
rev. 1.20 8 january 3, 2017 rev. 1.20 9 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu general description the device is flash memory a/d type 8-bit high performance assp architecture microcontrollers and specially designed for wireless power transmiss ion control . of fering users the convenience of flash memory multi-programming features, th is device also include s a wide range of functions and features. other memory includes an area of ram data memory as well as an area of true eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog feature include s a multi-channel 12-bit a /d converter and d igital feature includes d /a converter. multiple and extremely flexible t imer modules provide timing, pulse generation and pwm generation functions. communication with the outside world is catered for by including fully integrated i 2 c interface function, this popular interface which provide s designers with a means of easy communication with external peripheral hardware. protective features such as an internal watchdog t imer, low v oltage reset , over current protection and low v oltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt , hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate a nd swi tch d ynamically b etween a r ange o f o perating m odes u sing d ifferent c lock so urces gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of flexible i/o programming features, pll, ocp , demodulator , clock generator , reference volt age gene rator, time-base functi ons al ong wi th m any othe r fea tures ensure t hat the device will fnd excellent use in wireless power transmission applications. block diagram 8- bit risc mcu core i/o ocp flash program memory eeprom data memory flash/ eeprom programming circuitry time bases clock generator low voltage detect low v oltage reset interrupt controller reset circuit hxt oscillator 12- bit a /d converter ram data memory demo - dulation i 2 c timer modules watchdog timer hirc oscillator lirc oscillator internal reference voltage
rev. 1.20 8 january 3, 2017 rev. 1.20 9 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pin assignment pa3/an3/vref pc0/pwm0 pc1/pwm1 pa2/scl/an2/icpck/ocdsck pc2/pwm2 pc3/pwm3 pllcom comm0 avdd pa0/sda/an0/icpda/ocdsda ocp/an1 pc6/osc1 pc7/osc2 avss pc4/comm1/an pc5/comm2/ax pb1/cx pa6/an6/cp pa5/an5 pa4/an4 pa7/tck1/an7 pb3/scl/tp1_1 pb2/sda/tp1_0 vdd vss pb4/tp0/demo pb0/int1/tck0 pa1/cn HT66FW2230 28 ssop-a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pin descriptions pin name function opt i/t o/t description pa0/sda/ an0/icpda/ ocdsda pa0 papu pawu pas0 st cmos general purpose i/o. register enabled pull-up and wake-up. sda pas0 st o.d i 2 c data line an0 pas0 an adc input channel icpda st cmos icp data/address pin ocdsda st cmos ocds data/address, for ev chip only pa1/cn pa1 papu pawu pas0 st cmos general purpose i/o. register enabled pull-up and wake-up. cn pas0 an comparator input ocp/an1 ocp ocpc0 an ocp input an1 adcr0 an adc input channel pa2/scl/ an2/icpck/ ocdsck pa2 papu pawu pas0 st cmos general purpose i/o. register enabled pull-up and wake-up. scl pas0 st o.d i 2 c clock line an2 pas0 an adc input channel icpck st icp clock pin ocdsck st ocds clock pin, for ev chip only pa3/an3/ vref pa3 papu pawu pas0 st cmos general purpose i/o. register enabled pull-up and wake-up. an3 pas0 an adc input channel vref pas0 adcr1 an adc reference voltage input pa4/an4 pa4 papu pawu pas1 st cmos general purpose i/o. register enabled pull-up and wake-up. an4 pas1 an adc input channel
rev. 1.20 10 january 3, 2017 rev. 1.20 11 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pin name function opt i/t o/t description pa5/an5 pa5 papu pawu pas1 st cmos general purpose i/o. register enabled pull-up and wake-up. an5 pas1 an adc input channel pa6/ an6/ cp pa6 papu pawu pas1 st cmos general purpose i/o. register enabled pull-up and wake-up. an6 pas1 an adc input channel cp pas1 an comparator input pa7/tck1/ an7 pa7 papu pawu pas1 st cmos general purpose i/o. register enabled pull-up and wake-up. tck1 st tm clock input an7 pas1 an adc input channel pb0/int1/ tck0 pb0 rstc st cmos general purpose i/o. register enabled pull-up. int1 integ intc2 st external interrupt 1 tck0 st tm clock input pb1/cx pb1 pbpu pbs0 st cmos general purpose i/o. register enabled pull-up. cx pbs0 cmos comparator output pb2/sda / tp1_0 pb2 pbpu pbs0 st cmos general purpose i/o. register enabled pull-up. sda pbs0 st o.d i 2 c data line tp1_0 pbs0 st cmos tm1 i/o pb3/scl / tp1_1 pb3 pbpu pbs0 st cmos general purpose i/o. register enabled pull-up. scl pbs0 st o.d i 2 c clock line tp1_1 pbs0 st cmos tm1 i/o pb4/tp0/ int0/ demo pb4 pbpu pbs0 st cmos general purpose i/o. register enabled pull-up. tp0 pbs0 st cmos tm0 i/o int0 integ intc0 st external interrupt 0 demo pbs0 cmos demodulation output pc0/pwm0 pc0 pcpu pcs0 st cmos general purpose i/o. register enabled pull-up. pwm0 pcs0 cmos pwm0 pc1/pwm1 pc1 pcpu pcs0 st cmos general purpose i/o. register enabled pull-up. pwm1 pcs0 cmos pwm1 pc2/pwm2 pc2 pcpu pcs0 st cmos general purpose i/o. register enabled pull-up. pwm2 pcs0 cmos pwm2 pc3/pwm3 pc3 pcpu pcs0 st cmos general purpose i/o. register enabled pull-up. pwm3 pcs0 cmos pwm3 pc4/ comm1/ an pc4 pcpu pcs1 st cmos general purpose i/o. register enabled pull-up. comm1 dcmisc pcs1 an demodulation input an pcs1 an opa input
rev. 1.20 10 january 3, 2017 rev. 1.20 11 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pin name function opt i/t o/t description pc5/ comm2/ ax pc5 pcpu pcs1 st cmos general purpose i/o. register enabled pull-up. comm2 dcmisc pcs1 an demodulation input ax pcs1 ao opa output pc6/osc1 pc6 pcpu pcs1 st cmos general purpose i/o. register enabled pull-up. osc1 pcs1 an hxt pc7/osc2 pc7 pcpu pcs1 st cmos general purpose i/o. register enabled pull-up. osc2 pcs1 ao hxt comm0 comm0 dcmisc an demodulation input pllcom pllcom an pll compensation (flter) osc1 osc1 hxt oscillator input osc2 osc2 hxt oscillator output vdd vdd pwr digital positive power supply. vss vss pwr digital negative power supply. avdd avdd pwr analog positive power supply. avss avss pwr analog negative power supply. /hjhqg ,7 ,qsxw wsh 27 2xwsxw wsh 237 2swlrqdo e frqjxudwlrq rswlrq &2 ru uhjlvwhu rswlrq 3:5 3rzhu 67 6fkplww 7 uljjhu lqsxw &026 &026 rxwsxw 1 qdorj lqsxw slq 2' rshq gudlq 2 dqdorj rxwsxw absolute maximum ratings 6xsso 9 rowdjh 9 ss ss s od ss dd 6ud sudu sud sudu d u u ud o 6 u f ud s fi u eo d d d f d eddo dd yf fdo sud i yf d u f e o s ffd so d su o su u f d diif yf uodeo
rev. 1.20 12 january 3, 2017 rev. 1.20 13 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu d.c. characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =20mhz 4.0 5.5 v i dd1 operating current, normal mode, f sys =f h 5v no load, f h =20mhz, adc off, wdt enable 5.0 7.5 ma i dd2 operating current, slow mode, f sys = f l =lirc; f sub =lirc 5v no load, f sys =lirc, adc off, wdt enable 30 50 a i idle0 idle0 mode stanby current (lirc on) 5v no load, adc off, wdt enable, lvr disable 2.5 5.0 a i idle1 idle1 mode stanby current 5v no load, adc off, wdt enable, f sys =20mhz on 2.2 3.3 ma i sleep sleep mode stanby current (lirc on) 5v no load, adc off, wdt enable, lvr disable 2.5 5.0 a v il input low voltage for pa, pb, pc, intn, tpn 5v 0 1.5 v 0 0.2v dd v v ih input high voltage for pa, pb, pc, intn, tpn 5v 3.5 5.0 v 0.8v dd v dd v v lvr low voltage reset voltage lvr 2.1v @25?c -5% 2.1 +5% v lvr 2.55v @25?c -5% 2.55 +5% v lvr 3.15v @25?c -5% 3.15 +5% v lvr= 3.8v @25?c -5% 3.8 -5% v i oh1 i/o port source current (pa,pb,pc4~pc7) 5v v oh =0.9v dd -5 -10 ma i ol1 i/o port sink current (pa,pb,pc4~pc7) 5v v ol =0.1v dd 10 20 ma i oh2 i/o source current (pc0~pc3) 3v 16 32 ma 5v 40 80 i ol2 i/o sink current (pc0~pc3) 3v -16 -32 ma 5v -40 -80 r ph pull-high resistance for i/o ports 5v 10 30 50 k
rev. 1.20 12 january 3, 2017 rev. 1.20 13 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu a.c. characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 4.0v~5.5v 20 mhz f sub system clock (lirc) 5v ta = 25c -10% 32 +10% khz v lvr ~5.5v ta = -40c~85c -30% 32 +60% khz t timer tckn , tpn input pin pulse width 0.3 s t int interrupt pulse width 10 s t eerd eeprom read time 5v 2 4 t sys t eewr eeprom write time 5v 2 4 ms t sst system start-up timer period (wake-up from halt, f sys off at halt state) 5v f sys =f hxt 128 t sys 5v f sys =f lirc 2 t sys system start-up timer period (wake-up from halt, f sys on at halt state) 5v 2 t sys t rstd system reset delay time (power on reset, lvr, wdtc/ lvrc s/w reset) 5v 25 50 100 ms system reset delay time (wdt time-out reset) 5v 8.3 16.7 33.3 ms 1rwh w sys i 66 t 68 i sub a/d characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions av dd a/d converter operating voltage v lvr 5.5 v v adi a/d converter input voltage 0 v ref v v ref a/d converter reference voltage 2 av dd v dnl differential non-linearity 5v t adck =1.0s 1 2 lsb inl integral non-linearity 5v t adck =1.0s 2 4 lsb i adc additional power consumption if a/d converter is used 5v no load, t adck =0.5s 1.20 1.80 ma t adck a/d converter clock period 0.5 10 s t adc a/d conversion time (include sample and hold time) 12-bit a/d converter 16 t adck t ads a/d converter sampling time 4 t adck t on2st a/d converter on-to-start time 2 s
rev. 1.20 14 january 3, 2017 rev. 1.20 15 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pll electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions i pll power consumption 5v 1.5 ma f pll pll frequency deviation (hxt) 4.0~5.5v f pll =100k~220k, step=100hz 0.05 % t stb0 stable time (change frequency) 5v f pll =100k160k 2 3 ms t stb1 stable time (pll off : on) 5v 8 ms jitter pll timing jitter 5v 0.1 % ocp electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions i dem demodulation operating current 5v demen=1, da v ref =2.5v 480 710 a i ocp ocp operating current 5v ocpen=1, da v ref =2.5v 480 710 a comparator i comp comparator operating current 5v no load 30 60 a v cmpos1 input offset voltage 5v -15 +15 mv v cmpos2 input offset voltage 5v by calibration -8 +8 mv v hys hysteresis width 5v 20 40 60 mv v cm common mode voltage range 5v v ss v dd - 1.4v v t pd comparator response time 5v with 100mv overdrive 370 560 ns opa i opa opa operating current 5v no load 200 350 a v opos1 input offset voltage 5v -15 15 mv v opos2 input offset voltage 5v by calibration -4 +4 mv v cm common mode voltage range 5v v ss v dd - 1.4v v psrr power supply rejection ratio 5v 60 80 db cmrr common mode rejection ratio 5v 60 80 db sr slew rate +, slew rate - 5v 1.8 2.5 v/s gbw gain band width 5v 500 khz errg opa gain error 5v gain=1/5/10/15/20/30/40/50 -5 g +5 % dac for ocpref/demref i dac dac operating current 5v v ref =2.5v 250 300 a v ref =5v 500 600 a ro r2r output resistor 5v 10 k dnl dac differential nonlinearity 5v -0.5 +0.5 lsb inl dac integral nonlinearity 5v -1 +1 lsb
rev. 1.20 14 january 3, 2017 rev. 1.20 15 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu reference voltage electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions i bg additional power consumption if v bg reference with buffer is used 5v 200 300 a v bg reference voltage 5v ta=25c -3% 1.04 +3% v v ref reference voltage 5v ta=25c -3% 2.08 +3% v i opa opa operating current 5v no load 200 350 a power on reset electrical characteristics ta= 25?c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start voltage to ensure power-on reset 100 mv rr vdd v dd rising rate to ensure power-on reset 0.035 v/ms t por minimum time for v dd stays at v por to ensure power-on reset 1 ms
rev. 1.20 16 january 3, 2017 rev. 1.20 17 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to their internal system architecture . the device takes advantage of the usual features found within risc microcontrollers providing increased speed of operation and periodic performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or c all i nstructions. an 8-bi t wi de al u i s use d i n pra ctically a ll i nstruction se t ope rations, whi ch carries out arithme tic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplified by moving data through the accumulator and the alu. certain internal registers are implemented in the d ata m emory and can be directly or indirectly addressed. the simpl e addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d c ontrol system with m aximum reliability a nd fexibility. t his makes t he device suitable for l ow- cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either an hxt/hirc or lirc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute.
? ? ? ? ? system clock and pipelining for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications.
rev. 1.20 16 january 3, 2017 rev. 1.20 17 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu
? ? ? ? ? ? ? ? ? ? instruction fetching program counter during pro gram e xecution, t he progr am co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. program counter program counter high byte pcl register pc11~pc8 pcl7~pcl0 the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writeable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jum ps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer , and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced . this feature prevents stack overfow allowing the programmer to use the structure more easily . however , when the stack is full, a call subroutine instruction can still be exec uted whic h wi ll result in a st ack overfow . prec autions should be ta ken to avoid such cases which might cause unpredictable program branching. if the stack is overfow , the frst program counter save in the stack will be lost.
rev. 1.20 18 january 3, 2017 rev. 1.20 19 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu
arithmetic and logic unit C alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations: and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec ? branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti flash program memory the program memory is the locatio n where the user code or program is stored. for this device the program memory is flash type, which means it can be programmed and re-programmed a lar ge number o f t imes, a llowing t he u ser t he c onvenience o f c ode m odification o n t he sa me d evice. by using the appropriate programming tools, this flash device of fers users the flexibility to conveniently debug and develop their applications while also of fering a means of feld programming and updating. structure the progra m me mory ha s a c apacity of 4k16 bi ts. t he progra m me mory i s a ddressed by t he program counter and also contains data, table information and interrupt entries. t able data, which can be setup in any location within the program memory , is addressed by a separate table pointer register. special vectors within the program memory , certai n locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution.
rev. 1.20 18 january 3, 2017 rev. 1.20 19 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu
program memory structure look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register , tblp and tbhp . these registers defne the total address of the look-up table. after se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he pr ogram me mory u sing the t abrd[m] or t abrdl[m] instructions, respectively . when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data me mory r egister [ m] a s sp ecified i n t he i nstruction. t he h igher o rder t able d ata b yte f rom the program memory will be transferred to the tblh special register . any unused bits in this transferred higher order byte will be read as 0. the accompanying diagram illustrates the addressing data fow of the look-up table.

instruction table location bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 tabrd [m] @11 @10 @9 @8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: b11~b0: t able location bits @7~@0: t able pointer (tblp) bits @11~@8: t able pointer (tbhp) bits
rev. 1.20 20 january 3, 2017 rev. 1.20 21 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is f00h which refers to the start address of the last page within the 4k words program memory of the device. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address f06h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the t abrd [m] instruction is executed. because the tblh register is a read-only register and cannot be res tored, care should be taken to ensure its protection if both the main routine and interrupt s ervice routine us e table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a mov a,0fh ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address f06h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address f05h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 0f00h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : :
rev. 1.20 20 january 3, 2017 rev. 1.20 21 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu in circuit programming C icp the provision of flash type program memory provides the user with a means of convenient and easy upgrades a nd m odifcations t o t heir p rograms o n t he sa me d evice. as a n a dditional c onvenience, holtek has provided a means of programming the microcontroller in-circuit using a 4 -pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. the holtek flash mcu to w riter programming pin correspondence table is as follows: holtek write pins mcu programming pins function icpda pa0 programming serial data /address icpck pa2 programming clock vdd vdd power supply vss vss ground during the programming process, the user must there take care to ensure that no other outputs are connected to these two pins. the program memory and eeprom data memory can both be programmed serially in-circuit using this 4 -wire interface. data is downloaded and uploaded serially/parallel on several pins with an additional line for the clock. t wo additional lines are required for the power supply . the technical details regarding the in-circuit programming of the device is beyond the scope of this document and will be supplied in supplementary literature. during the programming process , the icpda and icpck pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins.
note: * may be resistor or capacito r. the resistance of * must be great er than 1k or the capacitance of * must be less than 1nf.
rev. 1.20 22 january 3, 2017 rev. 1.20 23 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu on-chip debug support C ocds there is an ev chip named ht66vw230 which is used to emulate the HT66FW2230 device. the ht66vw230 device also provides the on-chip debug function to debug the HT66FW2230 device during development proces s. the device, h t66fw2230, is almos t functional compatible except the on-chip debug function and package types. users can use the ht66vw230 device to emulat e the HT66FW2230 devic e behaviors by connecting the ocdsda and ocdsck pins to the holtek ht -ide development tools. the ocdsda pin is the ocds data/address input/output pin whi le t he ocdsck pi n i s t he ocds c lock i nput pi n. w hen use rs use t he ht 66vw230 e v chip for debugging, the corresponding pin functions shared with the ocdsda and ocdsck pins in the HT66FW2230 device will have no ef fect in the ht66vw230 ev chip. however , the two ocds pins which are pin-shared with the icp programming pins are still used as the flash memory programming pins for icp . for more detailed ocds information, refer to the corresponding document named holtek e-link for 8-bit mcu ocds users guide. holtek e-link pins ev chip pins mcu programming pins pin description ocdsda ocdsda pa0 on-chip debug support data/address input/output ocdsck ocdsck pa2 on-chip debug support clock input vdd vdd vdd power supply gnd vss vss ground ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. structure divided into two sections, the frst of these is an area of ram, known as the special function data memory. he re a re l ocated r egisters wh ich a re n ecessary f or c orrect o peration o f t he d evice. ma ny of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of data memory is known as the general purpose data memory , which is reserved for general purpose use. all locations within this area are read and write accessible under program control. the overall data memory is subdivided into two banks. the special purpose data memory registers are accessible in all banks, with the exception of the eec register at address 40h, which is only accessible in bank 1. switching between the dif ferent data memory banks is achieved by setting the bank pointer to the correct value. the start address of the data memory for the device is the address 00h. 00 h 7 fh 80 h ffh special purpose data memory general purpose data memory 128 bytes data memory structure
rev. 1.20 22 january 3, 2017 rev. 1.20 23 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu

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rev. 1.20 24 january 3, 2017 rev. 1.20 25 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu special function register description most of the special function register details will be described in the relevant functional section, however several registers require a separate description in this section. indirect addressing registers C iar0, iar1, iar2 the indirect addressing registers, iar0, iar1 and iar2, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0, iar1 and iar2 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory pointers, mp0, mp1l/mp1h or mp2l/mp2h. acting as a pair , iar0 and mp0 can together access data only from bank 0 while the iar1 register together with mp1l/mp1h register pair and iar2 register together with mp2l/mp2h register pair can access data from any data memory bank . as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1l, mp1h, mp2l, mp2h five memory pointers, known as mp0, mp1l, mp1h, mp2l and mp2h, are provided. these memory po inters a re p hysically i mplemented i n t he da ta me mory a nd c an b e m anipulated i n t he same way as normal registers providing a convenient way with which to address and track data. when any o peration t o t he r elevant i ndirect ad dressing r egisters i s c arried o ut, t he a ctual a ddress t hat t he microcontroller is directed to is the address specifed by the related memory pointer . mp0, together with indirect addressing register , iar0, are used to access data from bank 0, whi le mp1l/mp1h together with iar1 and mp2l/mp2h together with iar2 are used to access data from all data banks according to the corresponding mp1h or mp2h register . direct addressing can be used in all data banks using the corresponding instruction which can address all available data memory space. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 d b ? adres2 d b ? adres3 d b ? adres4 d b ? block d b ? code .section at 0 code org00h start : m ov a , 04h ; setup size of block m ov block , a m ov a , offset adres1 ; accumulator loaded with frst ram address m ov mp0 , a ; setup memory pointer with frst ram address loop : c lr iar0 ; clear the data at address defned by mp0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue : the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses.
rev. 1.20 24 january 3, 2017 rev. 1.20 25 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu accumulator C acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers C tblp, tbhp, tblh these three special function registers are used to cont rol operation of the look-up table which is stored i n t he progra m me mory. t blp a nd t bhp a re t he t able poi nters a nd i ndicate t he l ocation where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the sc, cz, zero flag (z), carry flag (c), auxiliary carry flag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/ logical o peration a nd sy stem m anagement fa gs a re u sed t o r ecord t he st atus a nd o peration o f t he microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the clr wdt or hal t instruction. the pdf fag is af fected only by executing the halt or clr wdt instruction or during a system power-up. the sc, cz, z, ov, ac and c fags generally refect the status of the latest operations. ? c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ? ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. ? z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ? ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared.
rev. 1.20 26 january 3, 2017 rev. 1.20 27 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ? pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. ? to is cleared by a system power-up or executing the clr wdt or halt instruction. t o is set by a wdt time-out. ? sc is the result of the xor operation which is performed by the ov fag and the msb of the current instruction operation result. ? cz is the operational result of different fags for different inst ructions. refer to register def ni- r uctions. refer to register def ni- uctions. refer to register defni - tions for more details. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. status register bit 7 6 5 4 3 2 1 0 name sc cz to pdf ov z ac c r/w r/w r/w r r r/w r/w r/w r/w por 0 0 "" unknown bit 7 sc: the result of the xor operation which is performed by the ov fag and the msb of the instruction operation result. bit 6 cz: the operational result of different fags for different inst uctions. for sub/subm instructions, the cz fag is equal to the z fag. for sbc/ sbcm instructions, the cz fag is the and operation result which is performed by the previous operation cz fag and current operation zero fag z . for other instructions, the cz fag will not be affected. bit 5 to: w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf: power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov: overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z: zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac: auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c: carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction.
rev. 1.20 26 january 3, 2017 rev. 1.20 27 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu eeprom data memory one of the s pecial features in the device is its internal eep rom d ata m emory. eep rom, w hich stands for electrically erasable programmable read only memory , is by its nature a non-volatile form of memory , with data retention even when its power supply is removed. by incorporating this kind of data mem ory, a whol e new host of appl ication possibi lities are ma de avail able to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specifc user data, system setup data or other product information to be stored directly within the product microcontroller . the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity is up to 648 bits. unlike the program memory and ram data memory , the eeprom data memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory . read and w rite operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. eeprom registers three registers control the overall operation of the internal eeprom data memory . these are the address register , eea, the data register , eed and a single control register , eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same way as any other special functi on regist er. the eec register however , be ing located in bank1, cannot be direct ly addressed directly and can only be read from or written to indirectly using the mp1l and mp1h memory pointers and indirect addres sing register , iar1. becaus e the eec control register is located at address 40h in bank 1, the mp 1l/mp2l memory pointer must frs t be set to the value 40h and the memory point, mp1h/mp2h, set to the value, 01h, before any operations on the eec register are executed. eeprom control registers list name bit 7 6 5 4 3 2 1 0 eea d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd eea register bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 ~ 0 data eeprom address data eeprom address bit 5 ~ bit 0
rev. 1.20 28 january 3, 2017 rev. 1.20 29 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu eed register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 data eeprom data data eeprom data bit 7 ~ bit 0 eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as "0" bit 3 wren: data eeprom w rite enable 0: disable 1: enable this is the d ata eep rom w rite enable bit w hich mus t be s et high before d ata eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr: eeprom w rite control 0: w rite cycle has fnished 1: activate a write cycle this i s t he da ta e eprom w rite c ontrol b it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no ef fect if the wren has not frst been set high. bit 1 rden: data eeprom read enable 0: disable 1: enable this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero w ill inhibit d ata eeprom read operations. bit 0 rd: eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the applic ation program will activ ate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no ef fect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time.
rev. 1.20 28 january 3, 2017 rev. 1.20 29 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu reading data from the eeprom to read data from the eep rom, the read enable bit, rden , in the eec register must frs t be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register . if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle term inates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register . the data will remain in the eed register until another read or write operation i s e xecuted. t he a pplication pr ogram c an po ll t he rd bi t t o de termine whe n t he da ta i s valid for reading. writing data to the eeprom to wr ite da ta t o t he e eprom, t he wr ite e nable bi t, w ren, i n t he e ec re gister m ust frst be se t high to enable the w rite function. the eep rom addres s of the data to be w ritten mus t then be placed in the eea register and the data placed in the eed register . if the wr bit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has fni shed c an be i mplemented e ither by pol ling t he w r bi t i n t he e ec re gister or by usi ng t he eeprom i nterrupt. w hen t he wr ite c ycle t erminates, t he w r b it wi ll b e a utomatically c leared t o zero by the microcontroller , informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on t he w rite e nable b it i n t he c ontrol r egister wi ll b e c leared p reventing a ny wr ite operations. also at power -on the mp1h/mp2h, will be re set to zero, which mea ns that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the w rite enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register . however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must als o be set. when an eeprom w rite cycle ends, the d ef reques t flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section.
rev. 1.20 30 january 3, 2017 rev. 1.20 31 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be periodic b y e nsuring t hat t he w rite e nable b it i s n ormally c leared t o z ero wh en n ot wr iting. al so the memory pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. when writing data the wr bit must be set high immediately after the wren bit has been set high, to ensure the write cycle executes correctly . the global interrupt bit emi should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. note that the devic e should not enter the idle or sleep mode until the eeprom read or write operation is totally complete. otherwise, the eeprom read or write operation will fail. programming examples ? reading data from the eeprom C polling method 029((3520b5(6 xvhughhgdgguhvv 029(( 029 vhwxsphprusrlwhu03 02903/ 03/srlwvwr((&uhjlvwhu 029 vhwxs 0hpru 3rlwhu 02903 6(7,5 vhw5(1elwhdeohuhdgrshudwlrv 6(7,5 vwduw5hdg&fohvhw5elw back: 6,5 fkhfhdffhh -03. 5,5 ldeh3520hdlh 503 02 hhdddhlh 025b ? writing data to the eeprom C polling method 029((3520b5(6 xvhughhgdgguhvv 029(( 029((3520b7 xvhughhggdwd 029(( 029 vhwxsphprusrlwhu03 02903/ 03/srlwvwr((&uhjlvwhu 029 vhwxs 0hpru 3rlwhu 02903 &/5(0, 6(7,5 vhw:5(1elwhdeohzulwhrshudwlrv 6(7,5 vwduw:ulwh&fohvhw:5elw 6(7(0, back: 6,5 fkhflhffhh -03. 5,5 ldeh3520lh 503
rev. 1.20 30 january 3, 2017 rev. 1.20 31 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu oscillator various oscillator confgurations of fer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through the registers. oscillator overview in additio n to being the source of the main system clock the oscillators also provide clock sources for the w atchdog t imer and t ime base interrupts. fully integrated inte rnal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. the h igher f requency o scillators p rovide h igher p erformance b ut c arry wi th i t t he d isadvantage o f higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capabilit y of dynamically switching between fast and slow system clock, the device has the fexibility to optim ize the performance/power ratio, a feature especially important in power sensitive portable applications. type name freq. external crystal hxt 20mhz internal high speed rc hirc 20mhz internal low speed rc lirc 32khz oscillator types system clock confgurations there are three methods of generating the system clock, two high speed oscillators and a low speed oscillator . the high speed oscillators are the external 20mhz crystal and internal 20mhz rc oscillators. the low speed oscillator is the internal 32khz (lirc) oscillator . selecting whether the low or high speed oscillator is used as the system oscillator is implem ented using the fhs bit and cks2~cks0 bits in the scc register and as the system clock can be dynamically selected. the actual source clock used for the high speed and the low speed oscillators is chosen via register . note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. hxt hirc f h lirc high speed oscillation low speed oscillation f h /2 f h / 16 f h / 64 f h /8 f h /4 f h / 32 fhs cks 2~ cks 0 f sys f sub mcd reset mcd f sub hxten hircen prescaler
rev. 1.20 32 january 3, 2017 rev. 1.20 33 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu external crystal/ ceramic oscillator C hxt the e xternal cryst al/ceramic syst em osc illator i s one of t he hi gh fre quency osc illator c hoices, which is selected via registers. for most crystal oscillator confgurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without r equiring e xternal c apacitors. ho wever, f or so me c rystal t ypes a nd f requencies, t o e nsure oscillation, it may be neces sary to add tw o small value capacitors, c1 and c2. us ing a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur . the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturers specifcation. for oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure thatthe c rystal a nd a ny a ssociated re sistors a ndcapacitors a long wi th i nterconnectinglines a re a ll located as close to the mcuas possible.
? ? ?? crystal/resonator oscillator C hxt internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has a fixed frequency of 20mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised . note that if this internal system clock is selected, as it requires no external pins for its operation. internal 32khz oscillator C lirc the internal 32khz system oscillator is the low frequency oscillator . it is a fully integrated rc osc illator wi th a t ypical fre quency of 32khz a t 5v , re quiring no e xternal c omponents for i ts implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised.
rev. 1.20 32 january 3, 2017 rev. 1.20 33 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu operating modes and system clocks present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conficting requirements that are especially true i n ba ttery powe red por table a pplications. t he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. as holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the devic e has many dif ferent clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock selections using register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency , f h , or low frequency , f sub , source, and is selected using the cks2~cks0 bits in the scc register . the high speed system clock can be sourced from eith er an hxt or hirc oscillator by confguring the fhs bit. the low speed system clock source can be sourced from the lirc oscillator . the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. hxt hirc f h lirc high speed oscillation low speed oscillation f h /2 f h / 16 f h / 64 f h /8 f h /4 f h / 32 fhs cks 2~ cks 0 f sys f sub mcd reset mcd f sub hxten hircen prescaler system clock confgurations note: when the system clock source f sys is switched to f sub from f h , the high speed oscillation will stop to conserve the power or continue to oscillate to provide the clock source, f h ~f h /64, for peripheral circuit to use, which is determined by confguring the corresponding high speed oscillator enable control bit.
rev. 1.20 34 january 3, 2017 rev. 1.20 35 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu system operation modes there are six dif ferent modes of operation for the microcontroller , each one with its own special characteristics and which can be chosen according to the specifc performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller , the normal mode and slow mode. the remaining four modes, the sleep , idle0, idle1 and idle2 mode are used when the microcontroller cpu is switched off to conserve power. operation mode cpu register setting f sys f h f sub fhiden fsiden cks2~cks0 normal on x x 000~110 f h ~f h /64 on on slow on x x 111 f sub off on idle0 off 0 1 000~110 off off on 111 on idle1 off 1 1 x on on on idle2 off 1 0 000~110 on on off 111 off sleep off 0 0 x off off on note : 1. in the idle mode, the system clock is turned on when bit cks[2:0]=000~110 and fhiden=1. 2. in the idle mode, the system clock is turned on when bit cks[2:0]=111 and fsiden=1. 3. in sleep mode, the lirc is turned on since the wdt is enabled. normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt or hirc oscillators. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. the clock source used will be from f sub . the f sub is derived from lirc. sleep mode the sleep mode is entered when an hal t instruction is executed and when the fhiden and fsiden bit are low . in the sleep mode the cpu will be stopped. however the f sub clock still can continue to operate because the wdt function is always enabled. idle0 mode the idle0 mode is entered when an hal t instruction is executed and when the fsiden bit in the scc register is high and the fhiden bit in the scc register is low . in the idle0 mode the cpu wi ll be swi tched of f but t he l ow spe ed osc illator wi ll be t urned on t o dri ve som e pe ripheral functions. idle1 mode the idle1 mode is entered when an hal t instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is high. in the idle1 mode the cpu will be switched of f but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational.
rev. 1.20 34 january 3, 2017 rev. 1.20 35 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu idle2 mode the idle2 mode is entered when an hal t instruction is executed and when the fhiden bit in the scc register is high and the fsiden bit in the scc register is low . in the idle2 mode the cpu will be switched of f but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. mcd (missing clock detector) function there is a missing clock detector , mcd, in this device. the mcd is used to detect the high speed oscillator operatio n when the corresponding oscillator is enabled. if the oscillator is enabled and no clock cycle is detected by the mcd in certain period of time, it mean s that the oscillator does not oscillate successfully and then the mcd will generate a signal to reset the microcontroller . control register the registers, scc, hxtc and hircc, are used to control the system clock within the device. scc register bit 7 6 5 4 3 2 1 0 name cks2 cks1 cks0 fhs fhiden fsiden r/w r/w r/w r/w r/w r/w r/w por 0 1 0 0 0 0 bit 7~5 cks2~cks0: the system clock selection 000: f h 001: f h /2 010: f h /4 011: f h /8 100: f h /16 101: f h /32 110: f h /64 111: f these three bits are used to select which clock is used as the system clock source. in addition to the system clock source directly derived from f h or f , a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 unimplemented, read as 0 bit 3 fhs: high frequency clock selection 0: hirc 1: hxt bit 2 unimplemented, read as 0 bit 1 fhiden: high frequency oscillator control when cpu is switched off 0: disable 1: enable this bit is used to control whether the high speed oscillator is activated or stopped when the cpu is switched off by executing an halt instruction. bit 0 fsiden: low frequency oscillator control when cpu is switched off 0: disable 1: enable this bi t i s use d t o cont rol whe ther t he l ow spe ed osc illator i s ac tivated or st opped when the cpu is switched of f by executing an hal t instruction. when the lirc oscillator i s se lected t o be t he l ow spe ed osc illator, t he l irc osc illator wi ll a lso be controlled by this bit together with the wdt function enable control bit. when this bit is cleared to 0, but the wdt function is enabled, the lirc oscillator will be enabled .
rev. 1.20 36 january 3, 2017 rev. 1.20 37 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu hxtc register bit 7 6 5 4 3 2 1 0 name hxtf hxten r/w r r/w por 0 0 bit 7~4 unimplemented, read as 0 bit 1 hxtf: hxt clock stable fag 0: unstable 1: stable this bit is used to indicate whether the hxt oscillator is stable or not. when the hxten bit is set to 1 to enable the hxt oscillator , the hxtf bit will be frst cleared to 0 and then set to 1 after the hxt oscillator is stable. bit 0 hxten: hxt oscillator enable control 0: disable 1: enable hircc register bit 7 6 5 4 3 2 1 0 name hircf hircen r/w r r/w por 0 1 bit 7~2 unimplemented, read as 0 bit 1 hircf: hirc clock stable fag 0: unstable 1: stable when the hirc oscillator is enabled and the hirc frequency is changed by application progra m, t his bi t wi ll frst be c leared t o 0 a nd t hen se t t o 1 a fter t he hirc oscillator is stable. bit 0 hircen: hirc oscillator enable control 0: disable 1: enable operating mode switching the devi ce c an swi tch bet ween opera ting m odes dynam ically a llowing t he use r t o se lect t he best performance/power ratio for the pres ent task in hand. in this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the cks2~cks0 bits in the scc register while mode switching from the normal/slow modes to t he sl eep/idle mode s i s e xecuted vi a t he hal t i nstruction. w hen a n hal t i nstruction i s executed, whet her t he de vice e nters t he idle mode or t he sle ep mode i s de termined by t he condition of the fhiden and fsiden bit in the scc register.
rev. 1.20 36 january 3, 2017 rev. 1.20 37 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu
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? ? ? normal mode to slow mode switching when r unning i n t he nor mal mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syste m c lock c an swit ch t o run i n t he sl ow mode by se t t he cks2~cks0 b its t o 111 i n t he sc c r egister. t his wi ll t hen u se t he l ow sp eed sy stem o scillator which wi ll c onsume l ess po wer. use rs m ay de cide t o do t his fo r c ertain op erations whi ch do no t require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lirc oscillator and therefore requires this oscillator to be stable before full mode switching occurs. slow mode to normal mode switching in slow mode the system clock is from f sub . when system clock is switched back to the normal mode from f sub , the cks2~cks0 bits should be set to 000 ~1 10 and then the system clock will respectively be switched to f h ~ f h /64. however, if f h is not used in slow mode, it will take some time to re-oscillate and stabilise. this is monitored using the hxtf/hircf bit in the hxtc/hircc register . the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used.
rev. 1.20 38 january 3, 2017 rev. 1.20 39 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu
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rev. 1.20 38 january 3, 2017 rev. 1.20 39 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu entering the sleep mode there is only one way for the device to enter the sleep mode and that is to execute the hal t instruction in the application program with both the fhiden and fliden bits in the scc register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the system clock will be stopped and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and resume counting . entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the hal t instruction in the application program with the fsiden bit in the scc register equal to 1 and the fhiden bit in the scc register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the f h clock will be stopped and the application program will stop at the halt instruction, but the f sub clock will be on. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt wi ll be cleared and resume counting . entering the idle1 mode there is only one way for the device to enter the idle1 mode and that is to execute the hal t instruction in the application program with both the fhiden and fliden bit in the scc register equal to 1. when this instruction is executed under the conditions described above, the following will occur: ? the f h and f sub clock will be on but the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports will maintain their present conditions. ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and resume counting.
rev. 1.20 40 january 3, 2017 rev. 1.20 41 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu entering the idle2 mode there is only one way for the device to enter the idle2 mode and that is to execute the hal t instruction in the application program with the fhiden bit in the scc register equal to 1 and the fliden bit in scc register equal to 0. when this instruction is executed under the conditions described above, the following will occur: ? the f h clock will be on but the f sub clock will be off and the application program will stop at the halt instruction. ? the data memory contents and registers will maintain their present condition. ? the i/o ports of peripheral device will keep to work when it is enabled and clock is from f sys . ? in the status register, the power down fag pdf will be set, and wdt timeout fag t o will be cleared. ? the wdt will be cleared and resume counting. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 and idle2 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to t he i/ o pi ns on t he de vice. al l hi gh-impedance i nput pi ns m ust be c onnected t o e ither a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumpti on. this also applies to devices which have dif ferent package types, as there may be unbonbed pins. these must eit her be set up as out puts or if setup as inputs must have pul l-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the lirc oscillator has enabled. in the idle1 and idle 2 mode the high speed oscillator is on, if the system oscillator is from the high speed oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps.
rev. 1.20 40 january 3, 2017 rev. 1.20 41 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu wake-up to minimise power consumption the device can enter the sleep or any idle mode, where the cpu will be switched of f. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resu me. system oscillator wake-up time sleep mode idle 0 mode idle 1 mode idle 2 mode hxt 1024 hxt cycles 1024 hxt cycles 1~2 hxt cycles 1~2 hxt cycles hirc 15~16 hirc cycles 15~16 hirc cycles 1~2 hirc cycles 1~2 hirc cycles lirc 1~2 lirc cycles 1~2 lirc cycles 1~2 lirc cycles 1~2 lirc cycles after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf fags. the pdf fag is cleared by a system power-up or executing the clear w atchdog t imer instructions and is set when executing the "hal t" instruction. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the p awu register to permit a negative transition on the pin to wake-up t he syste m. when a port a pin wake-up occurs, the progra m wil l resume exec ution at the instruction following the "hal t" instruction. if the system is woken up by an interrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag i s se t hi gh be fore e ntering t he sle ep or idl e mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. programming considerations the hxt , hirc and lirc oscillators use dif ferent sst counter . for example, if the system is woken up from the sleep mode and the hxt oscillator needs to start-up from an off state. ? if the device is woken up from the sleep mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after hircf/hxtf is "1". the same situation occurs in the power-on state. ? there a re p eripheral f unctions, su ch a s t ms, f or wh ich t he f sys i s u sed. i f t he sy stem c lock so urce is switched from f h to f sub , the clock source to the peripheral functions mentioned above will change accordingly.
rev. 1.20 42 january 3, 2017 rev. 1.20 43 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the w atchdog t imer clock source is sourced from lirc oscillators. the lirc internal oscillator has an approximate frequency of 32khz and this specifed internal clock period can vary with v dd , temperature and process variations. the w atchdog t imer source clock is then subdivided by a ratio of 2 8 to 2 18 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. watchdog timer control register a single register , wdtc, controls the required timeout period as well as the enable operation. the wdtc register is initiated to 01010011b at any reset (any reset includes por reset, lvr reset, lvr software reset, wdt time-out in cpu operating and wdt software reset) but keeps unchanged at the wdt time-out occurrence in a power down state. wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we2 we1 we0 ws2 ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~ 3 wdt function software control 10101 or 01010: enabled other values: reset mcu (reset will be active after 2~3 lirc clock for debounce time) if the mcu reset and it s caused by we[4:0] in wdtc software reset, the wrf fag in rstfc register will be set after reset. bit 2~ 0 wdt t ime-out period selection 000: 2 8 /f sub 001: 2 10 /f sub 010: 2 12 /f sub 011: 2 14 /f sub (default) 100: 2 15 /f sub 101: 2 16 /f sub 110: 2 17 /f sub 111: 2 18 /f sub these three bits determine the divis ion ratio of the w atchdog t imer s ource clock, which in turn determines the timeout period. rstfc register bit 7 6 5 4 3 2 1 0 name erstf lvrf wrf r/w r/w r/w r/w por 0 0 bit 7~ 4 unimplemented, read as 0 bit 3 reset caused by rst[7:0] setting describe elsewhere bit 2 lvr function reset fag describe elsewhere bit 1 unimplemented, read as 0
rev. 1.20 42 january 3, 2017 rev. 1.20 43 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu bit 0 wrf: reset caused by we[4:0] setting 0: not occur 1: occurred this bit is set to 1 by the wdt control register software reset and cleared by the application pr ogram. not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. watchdog timer operation the w atchdog t imer ope rates by provi ding a de vice re set whe n i ts t imer ove rfows. t his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he watchdog t imer before it overfows to prevent the w atchdog t imer from executing a reset. this is done using the clear watchdog instruction. if the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, th is clear instructio n will not be executed in the correct manner, in which case the w atchdog t imer will overfow and reset the device. w ith regard to the w atchdog t imer enable functio n, there are fve bits, we4~we0, in the wdtc register to of fer the e nable c ontrol a nd re set c ontrol of t he w atchdog t imer. t he w dt func tion wi ll be e nabled i f the we4~we0 bits are equal to 10101 or 01010b. if the we4~we0 bits are set to any other values, other than 01010b and 10101b, it will reset the device after 2~3 lirc clock cycles. after power on these bits will have a value of 01010b. we4 ~ we0 bits wdt function 01010b or 10101b enable any other value reset mcu watchdog timer enable/disable control under norm al progra m ope ration, a w atchdog t imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit t o. however , if the system is in the sleep or idle mode, when a w atchdog t imer time-out occurs, the t o bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the w atchdog t imer. the frst is a wdt software reset, which means a certain value except 01010b and 10101b written into the we4~we0 feld. the second is using the w atchdog t imer software clear instruction. the third is via a halt instruction. there is only one method of using software instruction to clear the w atchdog t imer. that is to use the single clr wdt instruction to clear the wdt contents. the maximum time out period is when the 2 18 division ratio is selected. as an example, with a 32 khz lirc os cillator as its s ource clock, this w ill give a maximum w atchdog period of around 8 second for the 2 18 division ratio, and a minimum timeout of 7.8ms for the 2 division ration.
rev. 1.20 44 january 3, 2017 rev. 1.20 45 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu clr wdt instruction 8-stage divider wdt prescaler we4~we0 bits wdtc register reset mcu f sub f sub /2 8 8-to-1 mux clr ws2~ws0 wdt time-out (2 8 /f sub ~ 2 18 /f sub ) halt instruction watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. t here is a number of other hardware and software reset sources that can be implemented dynamically when the device is running. reset overview the most importa nt reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the microcontroller , after a short delay , will be in a well defned state and ready to execute the frst program instruction. after this power -on reset, certain important internal registers will be set to defned states before the program comm ences. one of these registers is the program counter , which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. the devi ce provide s several reset sources to gene rate the interna l reset signal , provi ding extended mcu protection. the different types of resets are listed in the accompanying table. reset name abbreviation indication bit register notes power-on reset por auto generated at power on rstc register setting software reset erstf rstfc write to rstc register low-voltage reset lvr lrf rstfc low v dd voltage watchdog reset wdt to status wdt time-out wdtc register setting software reset wrf rstfc write to wdtc register mcd reset missing clock detector another type of reset is w hen the w atchdog t imer overflow s and resets the microcontroller . a ll types of reset operations result in dif ferent register conditions being setup. another reset exists in the form of a low v oltage reset which is implemented in situations where the power supply voltage falls below a certain threshold.
rev. 1.20 44 january 3, 2017 rev. 1.20 45 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu reset functions there are several ways in which a microcontroller reset can occur , through events occurring internally. power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. note: t rstd is power-on delay, typical time=50ms power-on reset timing chart rstc register software reset if the device reset caused by rst[7:0] setting, the erstf bit in the rstfc register will be set to 1. ? rstc external reset register bit 7 6 5 4 3 2 1 0 name rst7 rst6 rst5 rst4 rst3 rst2 rst1 rst0 r/w r/w r/w r/w r/w r r r/w r/w por 0 1 0 1 0 1 0 1 bit 7 ~ 0 rst7 ~ rst0: gpio or resb confguration selection for pb0 01010101 and 10101010 : confgured as gpio other v alues: mcu reset note: the device is fxed at pb0 before it leave s the factory. low voltage reset C lvr the micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. the l vr function is always enabled with a specifc l vr voltag e, v lvr . if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally and the l vrf bit in the rstfc register will also be s et to1. f or a valid l vr s ignal, a low voltage, i.e., a voltage in the range betw een 0.9v ~ v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed this value, the l vr will ignore the low supply voltage and will not perform a reset function. note that the l vr function will be automatically disable d when the device enters the power down mode. note: rstd is power-on delay, typical time=50ms low voltage reset timing chart
rev. 1.20 46 january 3, 2017 rev. 1.20 47 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ? lvrc register bit 7 6 5 4 3 2 1 0 name lvs7 lvs6 lvs5 lvs4 lvs3 lvs2 lvs1 lvs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 1 0 1 bit 2 ~ 0 lvs[7: 0]: lvr voltage select 01010101b: 2.1v (default) 00110011b: 2.55v 10011001b: 3.15v 10101010b: 3.8v any other value: generates mcu reset C register is reset to por value when an actual low voltage condition occurs, as specified by the above defined lvr voltage value, an mcu reset will be generated. the reset operation will be activated after 2~3 lirc clock cycles. in this situation this register contents will remain the same after such a set occurs. any uhjlvwhuydoxhrwkhuwkdqwkhirxughqhgydoxhvderyhzloodovruhvxowlqwkh generation of an mcu reset. the reset operation will be activated after 2~3 lirc clock cycles. however in this situation this register contents will be reset to the por value . ? rstfc register bit 7 6 5 4 3 2 1 0 name erstf lvrf wrf r/w r/w r/w r/w por 0 0 bit 7~ 4 unimplemented, read as 0 bit 3 erstf: reset caused by rst[7:0] setting 0: not active 1: active this bit can be clear to 0, but can not set to 1. bit 2 lvrf: lvr function reset fag 0: not active 1: active this bit can be clear to 0, but can not set to 1. bit 1 unimplemented, read as 0 bit 0 wrf: reset caused by we[4:0] setting describe elsewhere watchdog time-out reset during normal operation when t he w atchdog time-out reset during normal operation , the w atchdog time-out fag t o will be set to 1. note: t rstd is power-on delay, typical time=16.7ms wdt time-out reset during normal operation timing chart
rev. 1.20 46 january 3, 2017 rev. 1.20 47 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu watchdog time-out reset during sleep or idle mode the w atchdog time-out reset during sleep or idle mode is a little dif ferent from other kinds of re set. mo st of t he c onditions re main unc hanged e xcept t hat t he pro gram count er a nd t he st ack pointer will be cle ared to 0 and the t o fag will be set to 1. refer to the a.c. characteristics for t sst details. note: the t sst is 15~16 clock cycles if the system clock source is provided by hirc. the t sst is 128 clock cycles if the system clock source is provided by the hxt. the t sst is 1~2 clock for the lirc. wdt time-out reset during sleep or idle timing chart wdtc register software reset a wdtc software reset will be generated when a value other than 10101 or 01010, exist in the highest fve bits of the wdtc register . the wrf bit in the rstfc register will be set high when this occurs, thus indicating the generation of a wdtc software reset. ? wdtc register bit 7 6 5 4 3 2 1 0 name we4 we3 we2 we1 we0 ws2 ws1 ws0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 1 1 bit 7~ 3 wdt function software control 10101 or 01010: enabled other values: reset mcu (reset will be active after 2~3 lirc clock for debounce time) if the mcu reset and it s caused by we[4:0] in wdtc software reset, the wrf fag in rstfc register will be set after reset. bit 2~ 0 wdt t ime-out period selection described elsewhere
rev. 1.20 48 january 3, 2017 rev. 1.20 49 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he sl eep o r i dle mo de f unction o r w atchdog t imer. t he r eset f lags a re shown in the table: to pdf reset conditions 0 0 power-on reset u u lvr reset during normal or slow mode operation 1 u wdt time-out reset during normal or slow mode operation 1 1 wdt time-out reset during idle or sleep mode operation note: u stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer modules timer modules will be turned off input/output ports i/o ports will be setup as inputs and an0~an7 as a/d input pins stack pointer stack pointer will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. register reset (power on) wdt time-out (normal operation) wdt time-out (halt)* mp0 0000 0000 0000 0000 uuuu uuuu mp1l 0000 0000 0000 0000 uuuu uuuu mp1h 0000 0000 0000 0000 uuuu uuuu mp2l 0000 0000 0000 0000 uuuu uuuu mp2h 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu tbhp ---- xxxx ---- uuuu ---- uuuu status xx00 xxxx xx1u uuuu uu11 uuuu rstfc ---- 0x-0 ---- uu-u ---- uu-u rstc 0101 0101 0101 0101 uuuu uuuu wdtc 0101 0011 0101 0011 uuuu uuuu pscr ---- --00 ---- --00 ---- --uu tbc0 0--- -000 0--- -000 u--- -uuu tbc1 0--- -000 0--- -000 u--- -uuu lvrc 0101 0101 0101 0101 uuuu uuuu lvdc --00 -000 --00 -000 --uu -uuu integ ---- 0000 ---- 0000 ---- uuuu intc0 -000 0000 -000 0000 -uuu uuuu
rev. 1.20 48 january 3, 2017 rev. 1.20 49 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu register reset (power on) wdt time-out (normal operation) wdt time-out (halt)* intc1 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 uuuu uuuu mfi0 --00 --00 --00 --00 --uu --uu mfi1 --00 --00 --00 --00 --uu --uu mfi2 --00 --00 --00 --00 --uu --uu adrl (adrfs=0) xxxx ---- xxxx ---- uuuu ---- adrl (adrfs=1) xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=0) xxxx xxxx xxxx xxxx uuuu uuuu adrh (adrfs=1) ---- xxxx ---- xxxx ---- uuuu adcr0 0110 0000 0110 0000 uuuu uuuu adcr1 -000 0000 -000 0000 -uuu uuuu scc 010- 0-00 010- 0-00 uuu- u-uu hxtc ---- --00 ---- --00 ---- --uu hircc ---- --01 ---- --01 ---- --uu eea --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- uuuu pa 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 uuuu uuuu papu 0000 0000 0000 0000 uuuu uuuu pawu 0000 0000 0000 0000 uuuu uuuu pb ---1 1111 ---1 1111 ---u uuuu pbc ---1 1111 ---1 1111 ---u uuuu pbpu ---0 0000 ---0 0000 ---u uuuu pc 1111 1111 1111 1111 1111 uuuu pcc 1111 1111 1111 1111 1111 uuuu pcpu 0000 0000 0000 0000 0000 uuuu pas0 0000 0000 0000 0000 uuuu uuuu pas1 0000 0000 0000 0000 uuuu uuuu pbs0 0000 0000 0000 0000 uuuu uuuu pcs0 ---- 0000 ---- 0000 ---- uuuu ifs0 ---- ---0 ---- ---0 ---- ---u tm0c0 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --uu
rev. 1.20 50 january 3, 2017 rev. 1.20 51 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu register reset (power on) wdt time-out (normal operation) wdt time-out (halt)* iicc0 ---- 000- ---- 000- ---- uuu- iicc1 1000 0001 1000 0001 uuuu uuuu iicd xxxx xxxx xxxx xxxx uuuu uuuu iica 0000 000- 0000 000- uuuu uuu- i2ctoc 0000 0000 0000 0000 uuuu uuuu ckgen 0000 ---- 0000 ---- uuuu ---- pllfl 0000 0000 0000 0000 uuuu uuuu pllfh ---- -000 ---- -000 ---- -uuu pwmc 0101 0000 0101 0000 uuuu uuuu demc0 00-- 0000 00-- 0000 00-- uuuu demc1 x-00 0000 x-00 0000 u-uu uuuu demref 0000 0000 0000 0000 uuuu uuuu demacal 0010 0000 0010 0000 uuuu uuuu demccal 0001 0000 0001 0000 uuuu uuuu ocpc0 00-- ---- 00-- ---- 00-- ---- ocpc1 x-00 0000 x-00 0000 u-uu uuuu ocpref 0000 0000 0000 0000 uuuu uuuu ocpacal 0010 0000 0010 0000 uuuu uuuu ocpccal 0001 0000 0001 0000 uuuu uuuu dcmisc 000- --00 000- --00 uuu- --uu vrefc 0--- ---x 0--- ---x u--- ---u vracal 0010 0000 0010 0000 uuuu uuuu cpr 0--0 0000 0--0 0000 u--u uuuu note: "-" not implement u stands for unchanged x stands for unknown
rev. 1.20 50 january 3, 2017 rev. 1.20 51 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names p a, pb and pc. these i/o po rts a re m apped t o t he r am da ta me mory wi th spe cifc a ddresses a s sho wn i n t he spe cial purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instructio n mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. register name bit 7 6 5 4 3 2 1 0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pawu d7 d6 d5 d4 d3 d2 d1 d0 pb d4 d3 d2 d1 d0 pbc d4 d3 d2 d1 d0 pbpu d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selected using registers p apu~pcpu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit7~ bit 0 pull-high control 0: disable 1: enable pbpu register bit 7 6 5 4 3 2 1 0 name d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7~ 5 unimplemented, read as 0 bit 4 ~ 0 i/o port b bit 4~ bit 0 pull-high control 0: disable 1: enable
rev. 1.20 52 january 3, 2017 rev. 1.20 53 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pcpu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port c bit 7~ bit 0 pull-high control 0: disable 1: enable port a wake-up the hal t instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. v arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low . this function is especially suitable for applications that can be woken up via extern al switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 w ake up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as p ac~pcc, to control the input/output configuration. w ith this control register , each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~ 0 i/o port a bit 7 ~ bit 0 input/output control 0: output 1: input
rev. 1.20 52 january 3, 2017 rev. 1.20 53 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pbc register bit 7 6 5 4 3 2 1 0 name d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 bit 7~ 5 unimplemented, read as 0 bit 4 ~ 0 i/o port b bit 4 ~ bit 0 input/output control 0: output 1: input pcc register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~ 0 i/o port c bit 7 ~ bit 0 input/output control 0: output 1: input i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown.

??? ?? ? ? ? generic input/output structure
rev. 1.20 54 january 3, 2017 rev. 1.20 55 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu

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? ? ? ? - ? ? - ? ? ? ? a/d input/output structure pin-sharing functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these diffculties can be overcome. for some pins, the chosen function of the multi-function i/o pins is set by application program control. pas0 register bit 7 6 5 4 3 2 1 0 name pas07 pas06 pas05 pas04 pas03 pas02 pas01 pas00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas07~pas06: pa3 pin share setting 00: pa3 01: pa3 10: pa3 11: an3/vref ( determined by vrefs[1:0] ) bit 5~4 pas05~pas04: pa2 pin share setting 00: pa2 01: scl 10: pa2 11: an2 bit 3~2 pas03~pas02: pa1 pin share setting 00: pa1 01: pa1 10: cn 11: pa1 bit 1~0 pas01~pas00: pa0 pin share setting 00: pa0 01: sda 10: pa0 11: an0
rev. 1.20 54 january 3, 2017 rev. 1.20 55 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pas1 register bit 7 6 5 4 3 2 1 0 name pas17 pas16 pas15 pas14 pas13 pas12 pas11 pas10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pas17~pas16: pa7 pin share setting 00: pa7 01: pa7 10: pa7 11: an7 bit 5~4 pas15~pas14: pa6 pin share setting 00: pa6 01: pa6 10: cp/an6 11: an6 bit 3~2 pas13~pas12: pa5 pin share setting 00: pa5 01: pa5 10: pa5 11: an5 bit 1~0 pas11~pas10: pa4 pin share setting 00: pa4 01: pa4 10: pa4 11: an4 pbs0 register bit 7 6 5 4 3 2 1 0 name pbs07 pbs06 pbs05 pbs04 pbs03 pbs02 pbs01 pbs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pbs07~pbs06: pb4 pin share setting 00: pb4 01: tp0 10: demo 11: pb4 bit 5~4 pbs05~pbs04: pb3 pin share setting 00: pb3 01: tp1_1 10: tp1_1b 11: scl bit 3~2 pbs03~pbs02: pb2 pin share setting 00: pb2 01: tp1_0 10: tp1_0b 11: sda bit 1~0 pbs01~pbs00: pb1 pin share setting 00: pb1 01: pb1 10: cx 11: pb1
rev. 1.20 56 january 3, 2017 rev. 1.20 57 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pcs0 register bit 7 6 5 4 3 2 1 0 name pcs07 pcs06 pcs05 pcs04 pcs03 pcs02 pcs01 pcs00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pcs07~pcs06: pc3 pin share setting 00: pc3 01: pwm3 (=pwm13) 10: pwm3b (=pwm13b) 11: pc3 bit 5~4 pcs05~pcs04: pc2 pin share setting 00: pc2 01: pwm2 (=pwm12) 10: pwm2b (=pwm12b) 11: pc2 bit 3~2 pcs03~pcs02: pc1 pin share setting 00: pc1 01: pwm1 (=pwm11) 10: pwm1b (=pwm11b) 11: pc1 bit 1~0 pcs01~pcs00: pc0 pin share setting 00: pc0 01: pwm0 (=pwm10) 10: pwm0b (=pwm10b) 11: pc0 pcs1 register bit 7 6 5 4 3 2 1 0 name pcs17 pcs16 pcs15 pcs14 pcs13 pcs12 pcs11 pcs10 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 pcs17~pcs16: pc7 pin share setting 00: pc7 01: osc2 10: osc2 11: osc2 ( application note: its suggested to set as 0x11 for hxt ) bit 5~4 pcs15~pcs14: pc6 pin share setting 00: pc6 01: osc1 10: osc1 11: osc1 ( application note: its suggested to set as 0x11 for hxt ) bit 3~2 pcs13~pcs12: pc5 pin share setting 00: pc5 01: comm2 10: ax ( opa output ) 11: pc5 bit 1~0 pcs11~pcs10: pc4 pin share setting 00: pc4 01: comm1 10: an ( opa- ) 11: pc4
rev. 1.20 56 january 3, 2017 rev. 1.20 57 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ifs0 register bit 7 6 5 4 3 2 1 0 name ifs02 ifs01 ifs00 r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2 ifs02: i 2 c sda input source selection 0: pa0 1: pb2 bit 1 ifs01: i 2 c scl input source selection 0: pa2 1: pb3 bit 0 ifs00: tp0 input source selection 0: tp0 1: demo programming considerations within the user program, one of the frst things to consider is port initi alisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high selections have been chosen. if the port control registers, p ac~pcc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, p a~pc, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register o r b y p rogramming i ndividual b its i n t he p ort c ontrol re gister u sing t he set [m ].i a nd clr [m ].i i nstructions. not e t hat when usi ng t hese bi t c ontrol i nstructions, a re ad-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
read/w r ite timing port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function.
rev. 1.20 58 january 3, 2017 rev. 1.20 59 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. t o implement time related functions the device includes several t imer modules, abbreviated t o t he na me t m. t he t ms a re m ulti-purpose t iming un its a nd se rve t o pr ovide operations such as t imer/counter, input capture, compare match output and single pulse output as we ll a s be ing t he fun ctional uni t for t he ge neration of pw m si gnals. e ach of t he t ms ha s t wo individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the dif ferent tm types are described here with more detailed information provided in the individual standard and compact tm section. introduction the device contai ns a 10-bit standard tm and a 10-bit compact tm, each tm having a reference name of t m0 a nd t m1. al though si milar i n na ture, t he di fferent t m t ypes va ry i n t heir fe ature complexity. the common features to the s tandard and compact tm s w ill be des cribed in this section and the detailed operation w ill be described in corres ponding s ections. the main features and differences between the two types of tms are summarised in the accompanying table. function stm ctm timer/counter i/p capture compare match output pwm channels 1 1 single pulse output 1 pwm alignment edge edge pwm adjustment period & duty duty or period duty or period tm function summary tm0 tm1 10-bit stm 10-bit ctm tm name/type reference tm operation the t wo d ifferent t ypes o f t ms o ffer a d iverse r ange o f f unctions, f rom si mple t iming o perations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a fre e runni ng c ounter who se va lue i s t hen c ompared wi th t he va lue of pre -programmed i nternal comparators. when the free running counter has the same value as the pre-programmed comparator , known a s a c ompare m atch si tuation, a t m i nterrupt si gnal wi ll be ge nerated whi ch c an c lear t he counter a nd pe rhaps a lso c hange t he c ondition of t he t m ou tput pi n. t he i nternal t m c ounter i s driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the c lock so urce wh ich d rives t he m ain c ounter i n e ach t m c an o riginate f rom v arious so urces. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f sub clock source or the external tckn pin. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting.
rev. 1.20 58 january 3, 2017 rev. 1.20 59 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu tm interrupts the two different types of tms have two internal interrupts, the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. when a tm interrupt is generated, it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register . this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm i f se lected u sing t he t nck2~tnck0 b its. t he t m i nput p in c an b e c hosen t o h ave e ither a rising or falling active edge. the tms each have one or more output pins. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must frst be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type is different, the details are provided in the accompanying table. ctm o utput p in n ames h ave a _n su ffx. pi n n ames t hat i nclude a _0 o r _1 su ffx i ndicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. tm0 tm1 tp0 tp1_0, tp1_1 tm output pins tm input/output pin control register selecting t o ha ve a t m i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register, with a single bit in each register corresponding to a tm input/output pin.
tm0 function pin control block diagram
rev. 1.20 60 january 3, 2017 rev. 1.20 61 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu
tm1 function pin control block diagram note: 1. the i/o register data bits shown are used for tm output inversion control. 2. in the capture input mode, the tm pin control register must never enable more than one tm input. programming considerations the tm counter registers, the capture/compare ccra register, being both 10-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buf fer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. as t he ccra re gister i s i mplemented i n t he wa y shown i n t he fol lowing di agram a nd a ccessing these register pairs is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra low byte registers, named tmxal, using the following access procedures. accessing the ccra low byte register without following these access procedures will result in unpredictable values.

the following steps show the read and write procedures: ? writing data to ccra ? step 1. w rite data to low byte tmxal - note that here data is only written to the 8-bit buffer. ? step 2. w rite data to high byte tmxah - here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. ? reading data from the counter registers and ccra ? step 1. read data from the high byte tmxdh, tmxah - h ere d ata i s r ead d irectly f rom t he hi gh b yte r egisters a nd si multaneously d ata i s l atched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl or tmxal - this step reads data from the 8-bit buffer.
rev. 1.20 60 january 3, 2017 rev. 1.20 61 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu compact type tm C ctm although the simplest form of the two t m types, the compact t m type still contains three operating modes, wh ich a re c ompare ma tch ou tput, t imer/event c ounter a nd pw m ou tput m odes. t he compact t m c an a lso be c ontrolled wi th a n e xternal i nput pi n a nd c an dri ve t wo e xternal out put pins. these two external output pins can be the same signal or the inverse signal.
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? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? compact type tm block diagram (n=1) compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the onl y way of changi ng the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the t1on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur , a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.20 62 january 3, 2017 rev. 1.20 63 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu compact type tm register description overall operation of the compact tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tm1c0 t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 tm1c1 t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr tm1dl d7 d6 d5 d4 d3 d2 d1 d0 tm1dh d9 d8 tm1al d7 d6 d5 d4 d3 d2 d1 d0 tm1ah d9 d8 10-bit compact tm register list tm1dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl: tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1dh: tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm1al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al: tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 tm1ah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1ah: tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8
rev. 1.20 62 january 3, 2017 rev. 1.20 63 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu tm1c0 register bit 7 6 5 4 3 2 1 0 name t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau: tm1 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0: select tm1 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f 101: f 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm1. t he external pin clock source can be chosen to be active on the rising or falling edge. the clock source f is the system clock, while f h is the hxt oscillator and f is the internal clock, the details of which can be found in the oscillator section. bit 3 t1on: tm1 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm1. setting the bit high enables the counter to run, clearing the bit disables the tm1. clearing this bit to zero will stop the counter from counting and turn of f the tm1 which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value. if the tm1 is in the compare match output mode then the tm1 output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0: tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 1cclr bi t i s se t t o zero. set ting t he t 1cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.
rev. 1.20 64 january 3, 2017 rev. 1.20 65 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu tm1c1 register bit 7 6 5 4 3 2 1 0 name t1m1 t1m0 t1io1 t1io0 t1oc t1pol t1dpx t1cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1m1~t1m0: select tm1 operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t1m1 and t1m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t1io1~t1io0: select tp1_0, tp1_1 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tm1 output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm1 is running. in t he com pare ma tch out put mode , t he t 1io1 a nd t 1io0 bi ts de termine how t he tm1 output pin changes state when a compare match occurs from the comparator a. the t m1 ou tput pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pr esent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm1 output pin should be setup using the t1oc bit in the tm1c1 register . note that the output level requested by the t1io1 and t1io0 bits must be dif ferent from the initial value setup using the t1oc bit otherwise no change will occur on the tm1 output pin when a compare match occurs. after the tm1 output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t 1io1 a nd t 1io0 bi ts onl y a fter t he t m1 ha s be en swi tched of f. unpredictable pwm outputs will occur if the t 1io1 and t 1io0 bits are changed when the tm is running.
rev. 1.20 64 january 3, 2017 rev. 1.20 65 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu bit 3 t1oc: tp1_0, tp1_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm1 output pin. its operation depends upon whether tm1 is being used in the compare match output mode or in the pwm mode. it has no ef fect if the tm1 is in the t imer/counter mode. in the compare match output mode i t de termines t he l ogic l evel of he t m1 ou tput pi n be fore a c ompare match oc curs. in t he pwm mode i t det ermines i f t he pwm si gnal i s a ctive hi gh or active low. bit 2 t1pol: tp1_0, tp1_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1_0 or tp1_1 output pin. when the bit is set high the tm1 output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm1 is in the t imer/counter mode. bit 1 t1dpx: tm1 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this b it d etermines wh ich o f t he c cra a nd c crp r egisters a re u sed f or p eriod a nd duty control of the pwm waveform. bit 0 t1cclr: select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact t m1 c ontains t wo c omparators, c omparator a a nd c omparator p , e ither of which can be selected to clear the internal counter . w ith the t1cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm mode.
rev. 1.20 66 january 3, 2017 rev. 1.20 67 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu compact type tm operating modes the compact t ype tm can operate in one of three operating modes, compare match output mode, pwm mo de o r t imer/counter mo de. t he o perating m ode i s se lected u sing t he t 1m1 a nd t 1m0 bits in the tm1c1 register. compare match output mode to select this mode, bits t1m1 and t1m0 in the tm1c1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the t1cclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch o ccurs f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich allows the counter to overfow . here both t1af and t1pf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the t1cclr bit in the tm1c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t1cclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the t1af interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when a t1af interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t 1pf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he t1io1 and t1io0 bits in the tm1c1 register . the tm output pin can be selected using the t1io1 and t1io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he t1on bit changes from low to high, is setup using the t1oc bit. note that if the t1io1 and t1io0 bits are zero then no pin change will take place.
rev. 1.20 66 january 3, 2017 rev. 1.20 67 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu time output inverts when tnpol is high output controlled by other pin - shared function output pin reset to initial value output not affected by tnaf flag. remains high until reset by tnon bit here tnio1, tnio0 = 11 toggle output select now tnio1, tnio0 = 10 active high output select output pin set to initial level low if tnoc = 0 output toggle with tnaf flag ccra ccrp 0x 3ff counter overflow ccra int. flag tnaf ccrp int. flag tnpf ccrp > 0 counter cleared by ccrp value tm o/p pin tnon bit pause counter reset tncclr = 0; tnm[1:0] = 00 tnpau bit resume stop ccrp > 0 ccrp = 0 tnapol bit counter value compare match output mode C tncclr=0 note: 1. w ith tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. n= 1
rev. 1.20 68 january 3, 2017 rev. 1.20 69 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ccrp ccra 0x 3ff ccra = 0 counter overflows ccrp int. flag tnpf ccra int. flag tnaf ccra > 0 counter cleared by ccra value tm o/p pin tnon bit pause counter reset output pin reset to initial value output pin set to initial level low if tnoc = 0 output toggle with tnaf flag here tnio1, tnio0 = 11 toggle output select now tnio1, tnio0 = 10 active high output select tnpau bit resume stop time tnpf not generated no tnaf flag generated on ccra overflow output does not change ccra = 0 output inverts when tnpol is high tnpol bit tncclr = 1; tnm1, tnm0 = 00 output controlled by other pin - shared function output not affected by tnaf flag remains high until reset by tnon bit counter value compare match output mode C tncclr=1 note: 1. w ith tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 5. n= 1
rev. 1.20 68 january 3, 2017 rev. 1.20 69 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu timer/counter mode to select this mode, bits t1m1 and t1m0 in the tm1c1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits t1m1 and t1m0 in the tm1c1 register should be set to 10 respectively . the pwm functio n within the tm is useful for applications which require functions such as motor control, h eating c ontrol, i llumination c ontrol e tc. b y p roviding a si gnal o f f ixed f requency b ut of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pwm m ode, t he t 1cclr bi t ha s no e ffect on t he pwm operation. bot h of t he ccra a nd ccrp re gisters a re use d t o ge nerate t he pw m wave form, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the t1dpx bit in the tm1c1 register . the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t1oc bit in the tm1c1 register is used to select the required polarity of the pwm waveform while the two t1io1 and t1io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t1pol bit is used to reverse the polarity of the pwm output waveform. 10-bit ctm, pwm mode, edge-aligned mode, t1dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys =16mhz, tm clock source is f sys /4, ccrp=100b and ccra=128, the ctm pwm output frequency=(f sys /4)/512=f sys /2048=7.8125 khz, duty=128/512=25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit ctm, pwm mode, edge-aligned mode, t1dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.20 70 january 3, 2017 rev. 1.20 71 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ccrp ccra counter value counter cleared by ccrp ccra int. flag tnaf ccrp int. flag tnpf pwm output tm pin tnoc = 1 tnon bit pwm duty cycle set by ccra pwm period set by ccrp tnio1, tnio0 = 10 pwm output tnio1, tnio0 = 00 output inactive tnio1, tnio0 = 10 interrupts still generated here tnio1, tnio0 = 00 output forced to inactive level but pwm function keeps running internally tnio1, tnio0 = 10 resume pwm output counter stop if tnon bit low counter reset when tnon returns high pwm resumes operation time tnpol bit output inverts when tnpol = 1 tm pin tnoc = 0 tnpau bit resume pause tndpx = 0; tnm1, tnm0 = 10 output controlled by other pin - shared function pwm mode C tndpx=0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=1
rev. 1.20 70 january 3, 2017 rev. 1.20 71 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ccra ccrp counter value counter cleared by ccra ccrp int. flag tnpf ccra int. flag tnaf pwm output tm pin tnoc = 1 tnon bit pwm duty cycle set by ccrp pwm period set by ccra tnio1, tnio0 = 10 pwm output tnio1, tnio0 = 00 output inactive tnio1, tnio0 = 10 interrupts still generated here tnio1, tnio0 = 00 output forced to inactive level but pwm function keeps running internally tnio1, tnio0 = 10 resume pwm output counter stop if tnon bit low counter reset when tnon returns high pwm resumes operation time tnpol bit output inverts when tnpol = 1 tm pin tnoc = 0 tnpau bit resume pause tndpx = 1; tnm1, tnm0 = 10 output controlled by other pin - shared function pwm mode C tndpx=1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0]=00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n=1
rev. 1.20 72 january 3, 2017 rev. 1.20 73 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu standard type tm C stm the standard t ype tm contains fve operating modes, which are compare match output, t imer/ event counter , capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one external output pins. name tm no. tm input pin tm output pin 10-bit stm 0 tck0 tp0
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? ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? standard type tm block diagram (n=0) standard tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. t here a re a lso t wo i nternal c omparators wi th t he na mes, com parator a a nd com parator p. t hese c omparators wi ll c ompare t he v alue i n t he c ounter wi th c crp a nd c cra r egisters. t he ccrp is 3-bits wide whose value is compared with the highest 3 bits in the counter while the ccra is the 10 bits and therefore compares with all counter bits. the onl y way of changi ng the value of the 10-bit counte r using the appl ication program , is to clear the counter by changing the t2on bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when thes e conditions occur , a tm interrupt s ignal w ill als o us ually be generated. the s tandard type tm can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers.
rev. 1.20 72 january 3, 2017 rev. 1.20 73 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tm0c0 t0pau t0ck2 t0ck1 t0ck0 t0on t0rp2 t0pr1 t0pr0 tm0c1 t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr tm0dl d7 d6 d5 d4 d3 d2 d1 d0 tm0dh d9 d8 tm0al d7 d6 d5 d4 d3 d2 d1 d0 tm0ah d9 d8 10-bit standard tm register list tm0c0 register bit 7 6 5 4 3 2 1 0 name t0pau t0ck2 t0ck1 t0ck0 t0on t0rp2 t0pr1 t0pr0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t0pau: tm0 counter pause control 0: run 1: pause the c ounter c an be pa used by se tting t his bi t hi gh. cl earing t he bi t t o z ero re stores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t0ck2~t0ck0: select tm0 counter clock 000: f /4 001: f 010: f h /16 011: f h /64 100: f 101: f 110: tck0 rising edge clock 111: tck0 falling edge clock these three bits are used to select the clock source for the tm0. t he external pin clock source can be chosen to be active on the rising or falling edge. the cloc k source f is the system clock, while f h is the hx t oscillator and f is internal clock, the details of which can be found in the oscillator section. bit 3 t0on: tm0 counter on/off control 0: off 1: on this bit controls the overall on/of f function of the tm0. setting the bit high enables the counter to run, clearing the bit disables the tm0. clearing this bit to zero will stop the counter from counting and turn of f the tm0 which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. if the tm0 is in the compare match output mode then the tm0 output pin will be reset to its initial condition, as specifed by the t0oc bit, when the t0on bit changes from low to high.
rev. 1.20 74 january 3, 2017 rev. 1.20 75 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu bit 2~0 t0rp2~t0rp0: tm0 ccrp 3-bit register, compared with the tm0 counter bit 9~bit 7 comparator p match period 000: 1024 tm0 clocks 001: 128 tm0 clocks 010: 256 tm0 clocks 011: 384 tm0 clocks 100: 512 tm0 clocks 101: 640 tm0 clocks 110: 768 tm0 clocks 111: 896 tm0 clocks these three bits are used to setup the value on the internal ccrp 3-bit register , which are then compared with the internal counter s highest three bits. the result of this comparison c an be se lected t o c lear t he i nternal c ounter i f t he t 0cclr bi t i s se t t o zero. set ting t he t 0cclr bi t t o z ero e nsures t hat a c ompare m atch wi th t he ccrp values will reset the internal counter . as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value tm0c1 register bit 7 6 5 4 3 2 1 0 name t0m1 t0m0 t0io1 t0io0 t0oc t0pol t0dpx t0cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t0m1~t0m0: select tm0 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: t imer/counter mode these bits setup the required operating mode for the tm. t o ensure reliable operation the tm should be switched of f before any changes are made to the t0m1 and t0m0 bits. in the t imer/counter mode, the tm output pin control must be disabled. bit 5~4 t0io1~t0io0: select tp0 output function compare match output mode 00: no change 01: output low 10: output high 11: t oggle output pwm mode /single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp0 01: input capture at falling edge of tp0 10: input capture at falling/rising edge of tp0 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm0 output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm0 is running. in t he com pare ma tch out put mode , t he t 0io1 a nd t 0io0 bi ts de termine how t he
rev. 1.20 74 january 3, 2017 rev. 1.20 75 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu tm0 output pin changes state when a compare match occurs from the comparator a. the t m0 ou tput pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pr esent state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm0 output pin should be setup using the t0oc bit in the tm0c1 register . note that the output level requested by the t0io1 and t0io0 bits must be dif ferent from the initial value setup using the t0oc bit otherwise no change will occur on the tm0 output pin when a compare match occurs. after the tm0 output pin changes state it can be reset to its initial level by changing the level of the t0on bit from low to high. in the pwm mode, the t0io1 and t0io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function i s m odified b y c hanging t hese t wo b its. i t i s n ecessary t o o nly c hange t he values of t he t 0io1 a nd t 0io0 bi ts onl y a fter t he t m0 ha s be en swi tched of f. unpredictable pwm outputs will occur if the t 0io1 and t 0io0 bits are changed when the tm is running. bit 3 t0oc: tp0 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ /single pulse output mode 0: active low 1: active high this is the output control bit for the tm0 output pin. its operation depends upon whether tm0 i s b eing u sed i n t he c ompare ma tch ou tput mo de o r i n t he pw m mo de/single pulse output mode. it has no ef fect if the tm0 is in the t imer/counter mode. in the compare match output mode it determines the logic level of he tm0 output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t0pol: tp0 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp0 output pin. when the bit is set high the tm0 output pin will be inverted and not inverted when the bit is zero. it has no ef fect if the tm0 is in the t imer/counter mode. bit 1 t0dpx: tm0 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t0cclr: select tm0 counter clear condition 0: tm0 comparator p match 1: tm0 comparator a match this bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. re member t hat t he compact t m0 c ontains t wo c omparators, c omparator a a nd c omparator p , e ither of which can be selected to clear the internal counter . w ith the t0cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low , the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow . a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t0cclr bit is not used in the pwm mode, single pulse or input capture mode.
rev. 1.20 76 january 3, 2017 rev. 1.20 77 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu tm0dl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm0dl: tm0 counter low byte register bit 7~bit 0 tm0 10-bit counter bit 7~bit 0 tm0dh register C 10-bit stm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm0dh: tm0 counter high byte register bit 1~bit 0 tm0 10-bit counter bit 9~bit 8 tm0al register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm0al: tm0 ccra low byte register bit 7~bit 0 tm0 10-bit ccra bit 7~bit 0 tm0ah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm0ah: tm0 ccra high byte register bit 1~bit 0 tm0 10-bit ccra bit 9~bit 8 standard type tm operating modes the standard t ype tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or t imer/counter mode. the operating mode is selected using the t0m1 and t0m0 bits in the tm0c1 register. compare output mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register , should be set to 00 respectively . in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow , a compare matc h from comparator a and a compare match from comparator p . when the t0cclr bit is low , there are two ways in which the counter can be cleared. one is when a c ompare m atch f rom c omparator p , t he o ther i s wh en t he c crp b its a re a ll z ero wh ich a llows the c ounter t o ove rfow. he re bot h t 0af a nd t 0pf i nterrupt re quest fa gs for com parator a a nd comparator p respectively, will both be generated.
rev. 1.20 76 january 3, 2017 rev. 1.20 77 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu if the t0cclr bit in the tm0c1 register is high then the counter will be cleared when a compare match occurs from comparator a. however , here only the t0af interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when t0cclr i s h igh n o t 0pf i nterrupt r equest fa g wi ll b e g enerated. i n t he c ompare ma tch ou tput mode, the ccra can not be set to 0. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when a t0af interrupt request fag is ge nerated a fter a c ompare m atch oc curs from co mparator a. t he t 0pf i nterrupt re quest fl ag, generated from a compare match occurs from comparator p , will have no ef fect on the tm output pin. t he wa y i n wh ich t he t m o utput p in c hanges st ate a re d etermined b y t he c ondition o f t he t0io1 and t0io0 bits in the tm0c1 register . the tm output pin can be selected using the t0io1 and t0io0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from com parator a. t he i nitial c ondition of t he t m out put pi n, whi ch i s se tup a fter t he t0on bit changes from low to high, is setup using the t0oc bit. note that if the t0io1 and t0io0 bits are zero then no pin change will take place. time output inverts when tnpol is high output controlled by other pin - shared function output pin reset to initial value output not affected by tnaf flag. remains high until reset by tnon bit here tnio1, tnio0 = 11 toggle output select now tnio1, tnio0 = 10 active high output select output pin set to initial level low if tnoc = 0 output toggle with tnaf flag ccra ccrp 0x 3ff counter overflow ccra int. flag tnaf ccrp int. flag tnpf ccrp > 0 counter cleared by ccrp value tpna o/p pin tnon bit pause counter reset tncclr = 0; tnm[1:0] = 00 tnpau bit resume stop ccrp > 0 ccrp = 0 tnapol bit counter value compare match output mode C tncclr=0 note: 1. w ith tncclr = 0 a comparator p match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon bit rising edge 4. n = 0
rev. 1.20 78 january 3, 2017 rev. 1.20 79 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ccrp ccra 0x 3ff ccra = 0 counter overflows ccrp int. flag tnpf ccra int. flag tnaf ccra > 0 counter cleared by ccra value tm o/p pin tnon bit pause counter reset output pin reset to initial value output pin set to initial level low if tnoc = 0 output toggle with tnaf flag here tnio1, tnio0 = 11 toggle output select now tnio1, tnio0 = 10 active high output select tnpau bit resume stop time tnpf not generated no tnaf flag generated on ccra overflow output does not change ccra = 0 output inverts when tnpol is high tnpol bit tncclr = 1; tnm1, tnm0 = 00 output controlled by other pin - shared function output not affected by tnaf flag remains high until reset by tnon bit counter value compare match output mode C tncclr=1 note: 1. w ith tncclr = 1 a comparator a match will clear the counter 2. the tm output pin controlled only by the tnaf fag 3. the output pin reset to initial state by a tnon rising edge 4. the tnpf fags is not generated when tncclr = 1 5. n = 0
rev. 1.20 78 january 3, 2017 rev. 1.20 79 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu timer/counter mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register should be set to 1 1 respectively . the t imer/counter m ode operates in an identical w ay to the compare m atch o utput m ode generating the same interrupt fags. the exception is that in the t imer/counter mode the tm output pin is not used. therefore the above description and t iming diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits t0m1 and t0m0 in the tm0c1 register should be set to 10 respectively and also the t0io1 and t0io0 bits should be set to 10 respectively . the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform i s e xtremely fl exible. in t he pw m m ode, t he t 0cclr bi t ha s no e ffect a s t he pw m period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency , while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the t0dpx bit in the tm0c1 register. the pw m wa veform f requency a nd d uty c ycle c an t herefore b e c ontrolled b y t he v alues i n t he ccra and ccrp registers. an interrupt flag, one for each of the ccra and ccrp , will be generated when a compare match occurs from either comparator a or comparator p . the t0oc bit in the tm0c1 register is used to select the required polarity of the pwm waveform while the two t0io1 and t0io0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the t0pol bit is used to reverse the polarity of the pwm output waveform. 10-bit stm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001 010 011 100 101 110 111 000 period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 4mhz, tm clock source is f sys , ccrp = 010b and ccra =128, the stm pwm output frequency = f sys / (2256) = f sys /512 = 7.8125 khz, duty = 128/(2256) = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit stm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001 010 011 100 101 110 111 000 period ccra duty 128 256 384 512 640 768 896 1024 the pw m o utput p eriod i s d etermined b y t he c cra r egister v alue t ogether wi th t he t m c lock while the pwm duty cycle is defned by the ccrp register value.
rev. 1.20 80 january 3, 2017 rev. 1.20 81 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ccrp ccra counter value counter cleared by ccrp ccra int. flag tnaf ccrp int. flag tnpf pwm output tm pin tnoc = 1 tnon bit pwm duty cycle set by ccra pwm period set by ccrp tnio1, tnio0 = 10 pwm output tnio1, tnio0 = 00 output inactive tnio1, tnio0 = 10 interrupts still generated here tnio1, tnio0 = 00 output forced to inactive level but pwm function keeps running internally tnio1, tnio0 = 10 resume pwm output counter stop if tnon bit low counter reset when tnon returns high pwm resumes operation time tnpol bit output inverts when tnpol = 1 tm pin tnoc = 0 tnpau bit resume pause tndpx = 0; tnm1, tnm0 = 10 output controlled by other pin - shared function pwm mode C tndpx=0 note: 1. here tndpx = 0 - counter cleared by ccrp 2. a counter clear sets pwm period 3. the internal pwm function continues running even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 0
rev. 1.20 80 january 3, 2017 rev. 1.20 81 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ccra ccrp counter value counter cleared by ccra ccrp int. flag tnpf ccra int. flag tnaf pwm output tm pin tnoc = 1 tnon bit pwm duty cycle set by ccrp pwm period set by ccra tnio1, tnio0 = 10 pwm output tnio1, tnio0 = 00 output inactive tnio1, tnio0 = 10 interrupts still generated here tnio1, tnio0 = 00 output forced to inactive level but pwm function keeps running internally tnio1, tnio0 = 10 resume pwm output counter stop if tnon bit low counter reset when tnon returns high pwm resumes operation time tnpol bit output inverts when tnpol = 1 tm pin tnoc = 0 tnpau bit resume pause tndpx = 1; tnm1, tnm0 = 10 output controlled by other pin - shared function pwm mode C tndpx=1 note: 1. here tndpx = 1 - counter cleared by ccra 2. a counter clear sets pwm period 3. the internal pwm function continues even when tnio[1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation 5. n = 0 single pulse mode to se lect t his mode , bit s t0m1 and t 0m0 i n t he t m0c1 regi ster should be se t t o 10 respe ctively and also the t0io1 and t0io0 bits should be set to 1 1 respectively . the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output lead ing edge is a low to high transition of the t0on bit, which can be implemented using the application program. however in the single pulse mode, the t0on bit can also be made to automatically change from low to high using the external tck0 pin, which will in turn initiate the single pulse output. when the t0on bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the t0on bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the t0on bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a.
rev. 1.20 82 january 3, 2017 rev. 1.20 83 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu

? ? ? ? ? ?? ? ? ?? single pulse generation (n=0) ccra ccrp ccrp int. flag tnpf ccra int. flag tnaf tm pin tnoc = 1 tnon bit pulse width set by ccra tnio1, tnio0 = 11 no ccrp interrupt generated here tnio1, tnio0 = 00 output forced to inactive level but counter keeps running internally tnio1, tnio0 = 11 resume single pulse output counter stops by software counter reset when tnon returns high time tnpol bit output inverts when tnpol = 1 tm pin tnoc = 0 tnpau bit resume pause software trigger tckn pin cleared by ccra match tckn pin trigger auto. set by tckn pin software clear software trigger software trigger tnm1, tnm0 = 10; tnio1, tnio0 = 11 counter value counter stopped by ccra tnio1, tnio0 = 11 single pulse output tnio1, tnio0 = 00 output inactive single pulse mode note: 1. counter stopped by ccra match 2. ccrp is not used 3. the pulse is triggered by the tckn pin or setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. 6. n = 0 however a compare match from comparator a will also automatically clear the t0on bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the t0on bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the t0cclr and t0dpx bits are not used in this mode.
rev. 1.20 82 january 3, 2017 rev. 1.20 83 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu capture input mode to s elect this mode bits t0m1 and t0m0 in the tm 0c1 regis ter s hould be s et to 01 res pectively. this mode enables external s ignals to capture and s tore the pres ent value of the internal counter and c an t herefore be use d fo r a pplications suc h a s pu lse wi dth m easurements. t he e xternal si gnal is supplied on the tp0 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the t0io1 and t0io0 bits in the tm0c1 register . the counter is started when the t0on bit changes from low to high which is initiated using the application program. when the required edge transi tion appears on the tp0 pi n the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tp0 pin the counter will continue to free run until the t0on bit changes from high to low . when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a us eful method in measuring long pulse w idths. the t0io 1 and t0io 0 bits can select the active trigger edge on the tp0 pin to be a rising edge, falling edge or both edge types. if the tnio1 and t0io0 bits are both set high, then no capture operation will take place irrespective of what happens on the tp0 pin, however it must be noted that the counter will continue to run. as t he t p0 p in i s p in sh ared wi th o ther f unctions, c are m ust b e t aken i f t he t m i s i n t he i nput c apture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the t0cclr and t0dpx bits are not used in this mode. counter value yy ccrp tnon tnpau ccrp int . flag tnpf ccra int . flag tnaf ccra value time counter cleared by ccrp pause resume counter reset tnm [1:0 ] = 01 tm capture pin tpn _x xx counter stop tnio [1:0 ] value xx yy xx yy active edge active edge active edge 00 ? rising edge 01 ? falling edge 10 ? both edges 11 ? disable capture capture input mode note: 1. tnm[1:0] = 01 and active edge set by the tnio[1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. the tncclr bit is not used 4. no output function - tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. 6. n = 0
rev. 1.20 84 january 3, 2017 rev. 1.20 85 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however , to properly process these signals by a microcontroller , they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller , the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the device contains a n 8 -channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digita l value. two additional channel s are demodulation and ocp operational amplifer outputs , dem_opa_output and ocp_opa_output. input channels a/d channel select bits input pins 8+2 acs4~acs0 an0~an7, dem_opa_output, ocp_opa_output the accompanying block diagram shows the overall internal structure of the a/d converter , together with its associated registers.
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?? ? ? ? ? ? ?? ? ? a/d converter structure a/d converter register description overall opera tion of t he a/ d c onverter i s c ontrolled usi ng four regi sters. a rea d onl y regi ster pai r exists to store the adc data 12-bit value. the remaining two registers are control registers which setup the operating and control function of the a/d converter. name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d3 d2 d1 d0 adrl(adrfs=1) d7 d6 d5 d4 d3 d2 d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff acs4 acs3 acs2 acs1 acs0 adcr1 vbgen adrfs vrefs1 vrefs0 adck2 adck1 adck0 a/d converter register list
rev. 1.20 84 january 3, 2017 rev. 1.20 85 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu a/d converter data registers C adrl, adrh as the device contain s an internal 12-bit a/d converter , they require two data registers to store the converted va lue. t hese a re a hi gh byt e re gister, kno wn a s adr h, a nd a l ow by te re gister, kno wn as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompany ing table. d0~d1 1 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1 to control the function and operation of the a/d converter, three control registers known as adcr0, adcr1 are provided. these 8-bit regis ters defne functions such as the selection of which analog channel is connected to the internal a/d converter , the digitised data format, the a/d clock source as well as control ling the start function and monitoring the a/d converter end of conversion status. the acs4~acs0 bits in the adcr0 register defne the adc input channel number . as the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter . it is the function of the acs4 ~ acs0 bits to determ ine which analog channel input signals, dem_op a_output, ocp_op a_output or internal 1.04v is actually connected to the internal a/d converter. the p as0 control register contains the p as07~pas00 bits and p as1 control register contains the p as17~pas10 bit s whic h det ermine whic h pins on port a are used as anal og inputs for t he a/d c onverter i nput a nd wh ich p ins a re n ot t o b e u sed a s t he a/ d c onverter i nput. se tting t he corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/ o or ot her pi n-shared func tion. w hen t he pi n i s se lected t o be a n a/ d i nput, i ts ori ginal function whether it is an i/o or other pin-shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. adcr0 register bit 7 6 5 4 3 2 1 0 name start eocb adoff acs4 acs3 acs2 acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 0 bit 7 start: start the a/d conversion 0-->1-->0 : start 0-->1 : reset the a/d converter and set eocb to "1" this bit is used to initiate an a/ d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb: end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high.
rev. 1.20 86 january 3, 2017 rev. 1.20 87 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter . if the bit is set high then the a/d converter will be switched of f reducing the device power consumption. as the a/d converter will consume a limited amount of power , even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 ~ 0 acs4 ~ acs0: select a/d channel (when acs4 is 0) 00000: an0 00001: an1 00010: an2 00011: an3 00100: an4 00101: an5 00110: an6 00111: an7 01000: an8 ( dem_opa_output ) 01001~01111: an9 ( ocp_opa_output ) 1xxxx: bandgap v oltage these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 is set high then the internal v bg will be routed to the a/d converter. adcr1 register bit 7 6 5 4 3 2 1 0 name vbgen adrfs vrefs1 vrefs0 adck2 adck1 adck0 r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 vbgen: internal reference voltage circuit control 0: disable 1: enable this bit controls the internal bandgap circuit on/of f function to the a/d converter . when the bit is set high the bandgap reference voltage can be used by the a/d converter. if reference voltage is not used by the a/d converter and the l vr/lvd function is disable d then the bandgap reference circuit will be automatically switched off to conserve power . when reference voltage is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 adrfs: adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section.
rev. 1.20 86 january 3, 2017 rev. 1.20 87 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu bit 4 ~ 3 vrefs1~vref0: select adc reference voltage 00: internal adc power 01: external vref pin 1x: internal v ref these bits are used to select the reference voltage for the a/d converter . if these bits are 01 t hen t he a/ d c onverter re ference vol tage i s suppl ied on t he e xternal vre f pin. if these bits are set to 1x then the a/d converter reference voltage is supplied on t he i nternal vre f. if t hese b its a re se t t o 00 t hen t he i nternal re ference i s use d which is taken from the power supply pin a vdd. bit 2 ~ 0 adck2 ~ adck0: select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: f sub these three bits are used to select the clock source for the a/d converter. the st art bi t i n t he adcr0 re gister i s use d t o st art a nd re set t he a/ d c onverter. w hen t he microcontroller s ets this bit from low to high and then low again, an analog to digital convers ion cycle will be initiated. when the st art bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the st art bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit i n t he adcr0 regi ster i s use d t o i ndicate whe n t he ana log t o di gital conve rsion process is complete. this bit will be automatically set to 0 by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in t he i nterrupt c ontrol r egister, a nd i f t he i nterrupts a re e nabled, a n a ppropriate i nternal i nterrupt signal wil l be generated. thi s a/ d i nternal int errupt si gnal wi ll direct the progra m flow t o t he associated a/d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter , which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys . the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/ d clock source is determined by the system clock f sys , and by bits adck2~adck0, there a re so me l imitations o n t he m aximum a/ d c lock so urce sp eed t hat c an b e se lected. as t he recommended range of permissible a/d clock period, t adck , is from 0.5s to 10s, care must be taken for system clock frequencies. for example, if the system clock operates at a frequency of 5mhz, the adck2~adck0 bits should not be set to 000b, 001b or 1 10b. doing so will give a/ d clock periods that are less than the minimum a/d clock period or greater than the maximum a/d clock period which may result in inaccurate a/d conversion values. refer t o t he fol lowing t able for e xamples, wh ere va lues m arked wi th a n a sterisk * sh ow whe re, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period.
rev. 1.20 88 january 3, 2017 rev. 1.20 89 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 (f sub ) 5mhz 200ns* 400ns* 800ns 1.6s 3.2s 6.4s 12.8s* undefned 10mhz 100ns* 200ns* 400ns* 800ns 1.6s 3.2s 6.4s undefned 20mhz 50ns* 100ns* 200ns* 400ns* 800ns 1.6s 3.2s undefned a/d clock period examples controlling t he powe r on/ off func tion of t he a/ d c onverter c ircuitry i s i mplemented usi ng t he adoff bit in the adcr0 register . this bit must be zero to power on the a/d converter . when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay , as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the p as07~pas00 bits in the p as0 register or the pas17~pas10 bits in the p as1 register or , if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommende d that the adoff is set high to reduce power consumption when the a/d converter function is not being used. the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, vdd, or from an external reference sources supplied on pin vref , or from, an internal reference sources. the desired selection is made using the vrefs1~vrefs0 bits. as the vref pin is pin-shared with other functions, when the vrefs1~vref s 0 bits are set to 01, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of t he a/ d a nalog i nput pi ns a re pi n-shared wi th t he i/ o pi ns on por t a a s we ll a s ot her functions. the p as07~pas00 bits in the p as0 control register and the p as17~pas10 bits in the pas1 control register , determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if these bits for its corresponding pin are set to be correct values then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way , pins can be changed under program control to change their function between a/d inputs and other function s. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the p ac port control register to enable the a/d input as when the pas07~pas00 b its o r t he p as17~pas10 b its e nable a n a/ d i nput, t he st atus o f t he p ort c ontrol register will be overridden. the a/d converte r has its own reference voltage pin, vref , however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs1~vrefs0 bits in the adcr1 register. the analog input values must not be allowed to exceed the value of vref .

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rev. 1.20 88 january 3, 2017 rev. 1.20 89 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. ? step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. ? step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. ? step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr0 register. ? step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the pas07~pas00 bits in the pas0 register and the pas17~pas10 bits in the pas1 register. (an1does not need to be selected as a/d input, because it is only pin with ocp and these two pins are both as input pins) ? step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master inter rupt control bit, emi, and the a/d converter interrupt bit, ade, must both be set high to do this. ? step 6 the analog to digital conversion process can now be initialised by setting the st art bit in the adcr0 register from low to high and then low again. note that this bit should have been originally cleared to zero. ? step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register ca n be poll ed. the conversion proc ess is com plete when thi s bit goes l ow. when thi s occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method , if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardw are will begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. t he t ime t aken f or t he a/d conversion is 16 t adck where t adck is equal to the a/d clock period.
rev. 1.20 90 january 3, 2017 rev. 1.20 91 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu

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? ? ? - ? ? ? ? ? ? - a/d conversion timing programming considerations during m icrocontroller ope rations where t he a/d c onverter i s not be ing use d, t he a/d i nternal circuitry can be switched of f to reduce power consumption, by setting bit adoff high in the adcr0 r egister. w hen t his h appens, t he i nternal a/ d c onverter c ircuits wi ll n ot c onsume p ower irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the device contains a 12-bit a/d converter , its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or v ref divided by 4096. 1 lsb= (v dd or v ref ) / 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) / 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he a/ d conve rter. e xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 lsb below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level.

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rev. 1.20 90 january 3, 2017 rev. 1.20 91 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu a/d programming examples the following two programming examples illustrate how to setup and implement an a/d conversion. in t he fr st e xample, t he m ethod o f p olling t he e ocb b it i n t he adc r0 r egister i s u sed t o d etect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using an eocb polling method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0ffh ; setup pas0 to confgure pins an0 ,an2, an3 mov pas0,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : jmp st art_conversion ; start next a/d conversion
rev. 1.20 92 january 3, 2017 rev. 1.20 93 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu example: using the interrupt method to detect the end of conversion clr ade ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.04v clr adoff mov a,0ffh ; setup pas0 to confgure pins an0 , an2, an3 mov pas0,a mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set ade ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti
rev. 1.20 92 january 3, 2017 rev. 1.20 93 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom m emory e tc. or iginally d eveloped b y ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master/slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interf ace, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, i t i s t he m aster de vice t hat ha s ove rall c ontrol of t he bus. for t his de vice, wh ich onl y operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. it i s sugge sted t hat t he use r sha ll not e nter t he m icro proc essor t o hal t m ode by a pplication program during processing i 2 c communication. if the pin is confgured to sda or scl function of i 2 c interface, the pin is confgured to open-collect input/output port and its pull-up function can be enabled by programm ing the related generic pull- up control register.

rev. 1.20 94 january 3, 2017 rev. 1.20 95 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu i 2 c registers there are four control registers associated with the i 2 c bus, iicc0, iicc1, iica and i2ct oc and one d ata r egister, i icd. t he i icd register, i s u sed t o st ore t he d ata b eing t ransmitted a nd r eceived o n the i 2 c bus. before the microcontro ller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the iicd register . after the data is received from the i 2 c bus, the microcontroller can read it from the iicd register . any transmission or reception of data from the i 2 c bus must be made via the iicd register. register name bit 7 6 5 4 3 2 1 0 iicc0 i2cdbnc1 i2cdbnc0 i2cen iicc1 iichcf iichaas iichbb iichtx iictxak iicsrw iicrnic iicrxak iicd iicdd7 iicdd6 iicdd5 iicdd4 iicdd3 iicdd2 iicdd1 iicdd0 iica iica6 iica5 iica4 iica3 iica2 iica1 iica0 i2ctoc i2ctoen i2ctof i2ctos5 i2ctos4 i2ctos3 i2ctos2 i2ctos1 i2ctos0 i 2 c registers list iicc0 register bit 7 6 5 4 3 2 1 0 name i2cdbnc1 i2cdbnc0 i2cen r/w r/w r/w r/w por 0 0 0 bit 7~4 unimplemented, read as 0 bit 3~2 i2cdbnc1~i2cdbnc0: i 2 c debounce t ime selection 00: no debounce 01: 2 system clock debounce 10: 4 system clock debounce 11: 4 system clock debounce bit 1 i2cen: i 2 c enable 0: disable (gpio pin-shared with i 2 c is i/o function) 1: enable (gpio pin-shared with i 2 c is i 2 c function) bit 0 unimplemented, read as "0" 2 c function could be turned of f or turned on by controlling the related pin-sharing control bit which decides the function of the i/o ports pin-shared the pins sda and scl. when the i/o ports pin- shared the pins sda and scl are chosen to the functions other than sda and scl by pin-sharing control bit, i 2 c function is turned of f and its operating current will be reduced to a minimum value. in contrary , i 2 c function is turned on when the i/o ports pin-shared the pins sda and scl are chosen to the pins sda and scl by controlling pin-sharing control bit.
rev. 1.20 94 january 3, 2017 rev. 1.20 95 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu iicc1 register bit 7 6 5 4 3 2 1 0 name iichcf iichaas iichbb iichtx iictxak iicsrw iicrnic iicrxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 iichcf: i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the i ichcf fa g i s t he d ata t ransfer fa g. t his fa g wi ll b e z ero wh en d ata i s b eing transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. below is an example of the fow of a two-byte i 2 c data transfer. ? first, i 2 c slave device receive a start signal from i 2 c master and then iichcf bit is automatically cleared to zero. ? second, i 2 c slave device fnish receiving the 1st data byte and then iichcf bit is automatically set to one. ? third, user read the 1st data byte from iicd register by the application program and then iichcf bit is automatically cleared to zero. ? fourth, i 2 c slave device fnish receiving the 2nd data byte and then iichcf bit is automatically set to one and so on. ? finally, i 2 c slave device receive a stop signal from i 2 c master and then iichcf bit is automatically set to one. bit 6 iichaas: i 2 c bus address match fag 0: not address match 1: address match the iichass fag is the address match fag. this fag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. bit 5 iichbb: i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the iichbb fag is the i 2 c busy fag. this fag will be 1 when the i 2 c bus is busy which will occur when a st art signal is detected. the fag will be set to 0 when the bus is free which will occur when a stop signal is detected. bit 4 iichtx: select i 2 c slave device is transmitter or receiver 0: slave device is the receiver 1: slave device is the transmitter bit 3 iictxak: i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the iictxak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set iictxak bit to 0 before further data is received. bit 2 iicsrw: i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the ii csrw fl ag i s t he i 2 c sl ave r ead/write fl ag. t his fl ag de termines whe ther the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the iichaas fag is set high, the slave device will check the iicsr w fag to determine whether it should be
rev. 1.20 96 january 3, 2017 rev. 1.20 97 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu in transmit mode or receive mode. if the iicsr w fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the iicsrw fag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iicrnic: i 2 c running using internal clock control 0: i 2 c running using internal clock 1: i 2 c running not using internal clock the i 2 c module can run without using internal clock, and generate an interr upt if the i 2 c interrupt is enabled, which can be used in sleep mode, idle(slow) mode. bit 0 iicrxak: i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag the iicrxak fag is the receiver acknowledge fag. when the iicrxak fag is 0, it means that a acknowledge signal has been received at the 9th clock , after 8 bits of data have been transm itted. when the sl ave device in the transm it mode, the sla ve device checks the iicrxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the iicrxak fag is 1. when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the iicd register is used to store the data being transmitted and received. before the device writes data to the i 2 c bus, the actual data to be transmitted must be placed in the iicd register . after the data is received from the i 2 c bus, the device can read it from the iicd register . any transmission or reception of data from the i 2 c bus must be made via the iicd register. name iicdd7 iicdd6 iicdd5 iicdd4 iicdd3 iicdd2 iicdd1 iicdd0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7~0 iicdd7~iicdd0: i 2 c data buffer bit 7~bit 0 name iica6 iica5 iica4 iica3 iica2 iica1 iica0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x unknown bit 7~1 iica6~iica0: i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6 ~ bit 0. the iica register is the location where the 7-bit slave address of the slave device is stored. bits 7~ 1 of the iica register defne the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the iica register, the slave device will be selected. bit 0 unimplemented, read as "0"
rev. 1.20 96 january 3, 2017 rev. 1.20 97 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu
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? ? ? ? ? ? i 2 c block diagram i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and fnally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the iichaas bit in the iicc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the iichaas bit to determine whether the interrupt source originates from an address match or from the comple tion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/writ e bit whose value will be placed in the sr w bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must init ialise the bus, the following are steps to achieve this: ? step 1 set confgure the pin-shared i/o ports to i 2 c pin function. (scl and sd a ). ? step 2 set i2cen bit in the iicc0 register to 1 to enable the i 2 c bus. ? step 3 write the slave address of the device to the i 2 c bus address register iica. ? step 4 set the iice interrupt enable bit of the interrupt control register to enable the i 2 c interrupt and multi-function interrupt.
rev. 1.20 98 january 3, 2017 rev. 1.20 99 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu
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?? i 2 c bus initialisation flow chart i 2 c bus start signal the st art signal can only be generated by the master device connec ted to the i 2 c bus and not by the slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the iichbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c b us. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal wil l be generat ed. the next bit fol lowing the address, which is the 8th bit, defnes the read/write status and will be saved to the iicsr w bit of the iicc1 register . the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag iichaas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the iichaas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer . when a slave address is matche d, the device must be placed in either the transmit mode and then write data to the iicd register, o r i n t he r eceive m ode wh ere i t m ust i mplement a d ummy r ead f rom t he i icd r egister t o release the scl line.
rev. 1.20 98 january 3, 2017 rev. 1.20 99 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu i 2 c bus read/write signal the iicsr w bit in the iicc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver . if the iicsr w fag is 1 then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitte r. if the iicsr w fag is 0 then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the mas ter has trans mitted a calling addres s, any s lave device on the i 2 c bus , w hose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the iichaas fag is high, the addresses have matched and the slave device must check the iicsr w fag to determine if it is to be a transmitter or a receiver . if the iicsrw fag is high, the slave device should be setup to be a transmitter so the iichtx bit in the iicc1 register should be set to 1. if the iicsr w fag is low , then the microcontroller slave device should be setup as a receiver and the iichtx bit in the iicc1 register should be set to 0. i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. t he o rder o f se rial b it t ransmission i s t he msb fr st a nd t he l sb l ast. after receipt of 8-bits of data, the receiver must transmit an acknowle dge signal, level 0, before it can receive the next data byte. if the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the sda line to allow the master to send a st op signal to release the i 2 c bus. the corresponding data will be stored in the iicd register. if setup as a transmitter , the slave device must frst write the data to be transmitted into the iicd register . if setup as a receiver , the slave device must read the transmitted data from the iicd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as iictxak, o n t he 9 th c lock. t he sl ave d evice, wh ich i s se tup a s a t ransmitter wi ll c heck t he iicrxak bit in the iicc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master.
rev. 1.20 100 january 3, 2017 rev. 1.20 101 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu

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? - note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the iicd register, or in the receive mode where it must implement a dummy read from the iicd register to release the i 2 c scl line. i 2 c communication timing diagram
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? ?? ? ? ? ?? i 2 c bus isr flow chart
rev. 1.20 100 january 3, 2017 rev. 1.20 101 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu i 2 c time-out control in order to reduce the problem of i 2 c lockup due to reception of erroneous clock sources, a time-out function is provided. if the clock source to the i 2 c is not received then after a fxed time period, the i 2 c circuitry and registers will be reset. the t ime-out c ounter st arts c ounting on a n i 2 c bus start & address m atch c ondition, a nd is c leared b y a n sc l f alling e dge. b efore t he n ext sc l f alling e dge a rrives, i f t he t ime e lapsed i s greater than the time-out setup by the i2ct oc regis ter, then a time-out condition w ill occur . the time-out function will stop when an i 2 c stop condition occurs. when an i 2 c time-out counter overflow occurs , the counter w ill stop and the i2ct oen bit w ill be c leared t o z ero a nd t he i2ct of bi t wi ll be se t hi gh t o i ndicate t hat a t ime-out c ondition ha s occurred. the time-out condition will also generate an interrupt which uses the i 2 c interrupt vector . when an i 2 c time-out occurs, the i 2 c internal circuitry will be reset and the registers will be reset into the following condition: register after i 2 c time-out iicd, iica, iicc0 no change iicc1 reset to por condition i 2 c registers after time-out the i2ct of f ag can be cleared by the application program. there are 64 time-out periods w hich can be selected using bits in the i2ctoc register. the time-out time is given by the formula: ((1~64) 32) / f sub . this gives a range of about 1ms to 64ms. note also that the lirc oscillator is continuously enabled. i2ctoc register bit 7 6 5 4 3 2 1 0 name i2ctoen i2ctof i2ctos5 i2ctos4 i2ctos3 i2ctos2 i2ctos1 i2ctos0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 i 2 c t ime-out control 0: disable 1: enable bit 6 t ime-out fag (set by time-out and clear by software) 0: no time-out 1: time-out occurred bit 5~0 t ime-out defnition i 2 c time-out clock source is f sub /32. i 2 c time-out time is given by: ([i2ctos5 : i2ctos0]+1) (32/f sub )
rev. 1.20 102 january 3, 2017 rev. 1.20 103 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pll clock generator the devic e provi des a clock generat or output whic h ca n be used as a pw m dri ver si gnal. the accompanying b lock d iagram sh ows t he o verall i nternal st ructure o f t he clock ge nerator , t ogether with its associated registers. f hxt frequency output = 100k~220khz (duty 50%, step=100hz) /2 mux ckis= 0: f hxt /2 1: f hxt mux frequency output= 1mhz clock generator duty=50% clock generator output ckos= 0: 100k~220khz 1: 1mhz 10mhz clock generator 1 clock generator 2 clock generator block diagram 220pf 4.7nf 132k pllcom pllcom pin external circuit clock generator operation the generator clock, can come from either f hxt or f hxt /2 , and is selected using the ckis bit in the ckgen register . the pllen a nd f1me n bi ts i n t he ckgen re gister are use d t o control c lock generator 1 and clock generator 2 respectively . the output frequency of the clock generator 1 is within a range of 100k~220k(step=0.1khz) while the clock generator 2 output frequency is 1mhz. clock generator output can come from generator 1 output or generator 2 output which is selected by ckos bit in the ckgen register . t he output frequency of the clock generator 1 is selected by pllfl and pllfh registers. t he clock output can be used as pwm driver signal. the pwm0en~pwm2en bits in the pwmc register, determine whether the pwm output function is enabled. the accompanying waveform diagram shows the relationship between the clock generator output and pwm signal for different output pins . clock generator output pc0/pwm0 pc1/pwm0b pc2/pwm1 pc3/pwm2 oc (over current) clock generator output driver block diagram
rev. 1.20 102 january 3, 2017 rev. 1.20 103 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu clock generator pwm0, pwm1, pwm2 pwm0b clock generator and pwmn output waveform clock generator register description three registers control the overall operation of the clock generator . these are the generator overall control register , ckgen , the generator 1 frequency selection register s , pllfl and pllfh, and the pwm output control register, pwmc. ckgen register bit 7 6 5 4 3 2 1 0 name pllen f1men ckos ckis r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 pllen: pll c lock generator 1 enable 0: disable 1: enable bit 6 f1men: 1mhz c lock generator 2 enable 0: disable 1: enable bit 5 ckos: output clock source selection 0: from pll clock generator (100khz~220khz) 1: from 1mhz clock generator bit 4 ckis: input clock source selection 0: f hxt /2 1: f hxt bit 3 ~ 0 unimplemented, read as 0
rev. 1.20 104 january 3, 2017 rev. 1.20 105 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pllfl register bit 7 6 5 4 3 2 1 0 name pfq7 pfq6 pfq5 pfq4 pfq3 pfq2 pfq1 pfq0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pllfh register bit 7 6 5 4 3 2 1 0 name pfq10 pfq9 pfq8 r/w r/w r/w r/w por 0 0 0 pfq10 ~ pfq0: pll frequency control bit 0: 100khz 1:100.1khz 2: 100.2khz 3: 100.3khz 4: 100.4khz ... 254: 125.4khz 255: 125.5khz 256: 125.6khz 257: 125.7khz 1197: 219.7khz 1198: 219.8khz 1199: 219.9khz 1200: 220khz other v alues: 220khz pwmc register ( pwm control register) bit 7 6 5 4 3 2 1 0 name pmod3 pmod2 pmod1 pmod0 pwm3en pwm2en pwm1en pwm0en r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 0 1 0 0 0 0 bit 7~4 pmod3~pmod0: pwm mode 0101: mode 0 1010: mode 1 ( full bridge complementary pwm output with dead time) other values: mcu reset (prevent interference) bit 3~0 pwm3en/pwm2en/pwm1en/pwm0en: pwm3/pwm2/pwm1/pwm0 enable/ disable control 0: disable 1: enable
rev. 1.20 104 january 3, 2017 rev. 1.20 105 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pwm output control mode 0 clock generator pwm 00 , pwm 02 , pwm 03 pwm 01 clock generator output oc ( over current ) pwm 01 pwm 00 pwm 03 pwm 02 pwm 11 pwm 10 pwm 13 pwm 12 pwm1en pwm0en pwm3en pwm2en mode 1 (protection mechanism is only existed in mode1) clock generator t d t d t d t d clock generator output oc ( over current ) pwm 01 pwm 00 pwm 03 pwm 02 pwm 11 pwm 10 pwm 12 pwm 01 pwm 00 pwm 03 pwm 02 pwm0en pwm 13 protection : avoid acting simultaneously
rev. 1.20 106 january 3, 2017 rev. 1.20 107 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu cpr register (complementary pwm control register) bit 7 6 5 4 3 2 1 0 name wrprt dtpsc1 dtpsc0 dt2 dt1 dt0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~5 wrpr t : w rite protection for pcs0, pcs1 and pwmc registers 0: these registers are writable 1: these registers cant be changed by writing bit 4~3 dtpsc[1: 0]: dead t ime prescaler 00: f =f h /1 01: f =f h /2 10: f =f h /4 11: f =f h /8 bit 2~0 dt2~dt0: dead time =1/f 000: dead time is [(1/f )-(1/f h )] ~ (1/f ) 001: dead time is [(2/f )-(1/f h )] ~ (2/f ) 010: dead time is [(3/f )-(1/f h )] ~ (3/f ) 011: dead time is [(4/f )-(1/f h )] ~ (4/f ) 100: dead time is [(5/f )-(1/f h )] ~ (5/f ) 101: dead time is [(6/f )-(1/f h )] ~ (6/f ) 110: dead time is [(7/f )-(1/f h )] ~ (7/f ) 111: dead time is [(8/f )-(1/f h )] ~ (8/f )
rev. 1.20 106 january 3, 2017 rev. 1.20 107 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu demodulation function the demodulator demodulates the communication signal from the receiver end. opa cmp comm 0 2.2m 100 k 0.1 uf 10 k 4.7 nf 4.7 nf 10 k 10 k 680 k 100 k signal after demodulation ( bias 2v) ht 66 fw2230 an ax cp cn cx filter interrupt comm 0 analog mux comm 1 comm 2 demo pad mcu reading ais [1:0] 8 bit dac c d[7:0] filter filter clock r1 r2 a (r1=4k) g=1/5/ 10 / 15 / 20 / 30 / 40 / 50 s1 s0 s2 s3 g[2:0] flt [2:0 ] f flt =f h /4 m[1:0] an 8 an ax cp cn cx dm s3 dm s2 dm s1 dm s0 demodulator circuit demodulator circuit operation t he demodulator input is sourced from comm0~comm2 , selected using the ais1~ais0 bits in the dcmisc register . after this, four switches s0~s3 , are used for mode selection . an op amp and two resistors are used to form a pga function . the pga gain can be positive or negative determine d by the input voltage connect ed to the positive input or negative input of the pga. demref is used to generate reference voltage. the comparator compares this reference voltage with the amplif ed output . f inally t he c omparator out put is fi ltered to ge nerate de mo a nd de mint . t hese a re debounced versions of demcx which are used to indicate whether the source current is outwith the specifcation or not. demo is defned as the demodulat or output and demint is the demodulat or interrupt trigger. note that the flter clock; f hxt is the hxt clock. the amplifed output voltage also can be read out by means of another adc from demax. the dac output voltage is contro lled by the demref register and the dac output is defned as dac v out = (dac v ref /256) demr ef [7:0] (1)
rev. 1.20 108 january 3, 2017 rev. 1.20 109 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu input voltage range the i nput vol tage c an be posi tive or ne gative, which together wi th the pga ope rating m ode, provides for a more fexible application. (1) if v in > 0 and the pga operates in the non - inverting mode, the output voltage of the pga is in pga vrr vo += )/1( 12 (2) (2) when the pga operates in the non-invert mode, also provides a unity gain buffer function. if dem[1:0]= 01 and demg[2:0]=000, the pga gain will be 1 and is configured as unity gain buffer. witches s2 and s3 will be open internally and the output voltage of the pga is in pga vvo = (3) (3) if 0 > v in > -0.7 v and the pga operates in the invert mode, the output voltage of the pga is in pga vrr vo ?= )/( 12 (4) note: if v in is negative, it should not be lower than - 0.7v to avoid leakage current. offset calibration the demodulation circuit has 4 operating mode s controlled by dem1~dem0 . one of these modes is the calibration mode (0 v input mode). in the calibration mode, the op and comparator of fset can be calibrated. opamp calibration: ? step1: set dem [1:0] =11, demaofm=1, the demodulat or is now in the opamp calibration mode. ? step2: set demaof [4:0] =00000 then read the demax bit status . ? step3: let demaof=demaof+1 then read the demax bit status ; if demax is changed , record the register data as vos1 . ? step4: set demaof [4:0] 111111 then read the demax bit status . ? step5: let demaof=demaof-1 then read the demax bit status ; if demax is changed , record the register data as vos2 . ? step6: restore vos = (vos1 + vos2)/2 to the demaof register . the calibration is now fnished. comparator calibration: ? step1: set dem [1:0] =11, demcofm=1, the ocp is now in the comparator calibration status . ? step2: set demcof [4:0] =00000 then read the demcx bit status . ? step3: let demcof=demcof+1 then read the demcx bit status ; if demcx is changed , record the register data as vos1 . ? step4: set demcof [4:0] =11111 then read the demcx bit status . ? step5: let demcof=demcof-1 then read the demcx bit status ; if demcx data is changed , record the register data as vos2. ? step6: restore vo s = (vos1 + v os2)/2 to the demcof register . the calibration is now fnished.
rev. 1.20 108 january 3, 2017 rev. 1.20 109 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu demodulator register description the demc0 and demc1registers are demodulat or control registers which control the demodulat or operation mode, pga and flter functions. the demref r egister is used to provide the reference voltages for t he de modulat or . de macal a nd de mccal a re use d t o c ancel out t he ope rational amplifer and comparator input offset. demc0 register bit 7 6 5 4 3 2 1 0 name dem1 dem0 dms3 dms2 dms1 dms0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 dem[1:0] : mode selection 00: demodulation function disable, s1, s3 on , s0,s2 off 01: demodulation function enable in non-inverter mode, s0, s3 on , s1,s2 off 10: demodulation function enable in inverter mode , s1, s2 on , s0,s3 off 11: demodulation function enable in 0v input mode, s1, s3 on , s0,s2 off note: disable means opa, cmp, dac, filter all off & cmp output=low. bit 5~4 unimplemented, read as 0 bit 3 dms3: demodulation switch 3 control (dms3) 0: off (disable 8-bit dac if dms3=1) 1: on bit 2 dms2: demodulation switch 2 control (dms2) 0: off 1: on bit 1 dms1: demodulation switch 1 control (dms1) 0: off 1: on bit 0 dms0: demodulation switch 0 control (dms0) 0: off 1: on
rev. 1.20 110 january 3, 2017 rev. 1.20 111 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu demc1 register bit 7 6 5 4 3 2 1 0 name demo demg2 demg1 demg0 demflt2 demflt1 demflt0 r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 dem o : demo output (read only) bit 6 unimplemented, read as 0 bit 5~3 demg2~demg0: opa gain i nverter mode: 000: -1 001: -5 010: -10 011: -15 100: -20 101: -30 110: -40 111: -50 non-inverter mode: 000: 1 001: 6 010: 1 1 011: 1 6 100: 2 1 101: 3 1 110: 4 1 111: 5 1 bit 2~0 demflt2~demflt0: demodula tor flter selection 000: 0 t flt ( without flter) 001: 1~2 t flt 010: 3~4 t flt 011: 7~8 t flt 100: 15~16 t flt 101: 31~32 t flt 110: 63~64 t flt 111: 127~128 t flt note: t flt = f h /4, f h =f hxt (crystal) , t flt =1/f flt demref register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 demref: select reference voltage for over current protect reference v oltage= (d/a reference voltage/256) (n) , n=demr[7:0 ]
rev. 1.20 110 january 3, 2017 rev. 1.20 111 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu demacal register bit 7 6 5 4 3 2 1 0 name demaofm demars demaof5 demaof4 demaof3 demaof2 demaof1 demaof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 demaofm: input offset voltage cancellation mode or normal operating mode selection 0: normal operating mode 1: input offset voltage cancellation mode bit 6 demars: input offset voltage cancellation reference selection bit 0: select negative input as the reference input 1: select positive input as the reference input bit 5~0 demaof5~demaof0: input offset voltage calibration control demccal register bit 7 6 5 4 3 2 1 0 name demaxcx demcofm demcrs demcof4 demcof3 demcof2 demcof1 demcof0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 demaxcx: opa/ comparator output for calibration ; positive logic (read only) i f demaofm=1, this bit is the opa output for calibration i f demcofm=1, this bit is the comparator output for calibrationr note: demaofm and demcofm can t be 1 simultaneously. bit 6 demcofm: input offset voltage cancellation mode or normal operating mode selection 0: normal operating mode 1: input offset voltage cancellation mode bit 5 demcrs: input offset voltage cancellation reference selection bit 0 : select negative input as the reference input 1 : select positive input as the reference input bit 4~0 demcof4 ~ demcof0: input offset voltage calibration control
rev. 1.20 112 january 3, 2017 rev. 1.20 113 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ocp function ocp is an abbreviation for over current protect ion . the ocp detect s an input voltage which is proportional to the monitored source current. if the input voltage is lar ger than the reference voltage set by the dac, the ocp will generate an output signal to indicate that the source current is outwith the specifcation. ocp/an1 interrrupt (ocf) oc for pwm output disable & mcu reading an1 8 bit dac c ocpref[7:0] filter filter clock r1 r2 a (r1=4k) g=1/5/10/15/20/30/40/50 s1 s0 s2 s3 f flt =f h /4 ocpm[1:0] an9 ocpg[2 0] ocpflt[2 0] ocpax ocpcx ocpo over current protect circuit ocp circuit operation the source voltag e is sourced from the ocp. f our switches s0~s3 form of a mode select function. an operational amplifier and two resistors form a pga function . the pga gain can be positive or negative determine d by the input voltage connect ed to the positive input or negative input of the pga. the ocpref is used to generate a reference voltage. the comparator compares the reference voltage and the amplified output voltage . finally the comparator output is filtered t o generate the ocp o ou tput to di sable t he pw m ou tput a nd the ocp i nterrupt t rigger . t hese a re debounced versions of demcx which are used to indicate whether the source current is outwith the specifcation or not. note that the flter clock; f hxt is the hxt clock. the amplifed output voltage also can be read out by means of another adc from ocp ax. the dac output voltage is controlled by the ocpref register and the dac output is defne d as dac v out = (dac v ref /256) ocpref[7:0] (1) input voltage range the i nput vol tage c an be posi tive or ne gative, which together wi th the pga ope rating m ode, provides for a more fexible application. (1) if v in > 0 and the pga operates in the non - inverting mode, the output voltage of the pga is in pga vrr vo += )/1( 12 (2) (2) when the pga operates in the non-invert er mode, it also provides a unity gain buffer function. if ocpm[1:0]= 01 and ocpg[2:0]=000, the pga gain will be 1 and is confgured as a unity gain buffer. s witches s2 and s3 will be open internally and the output voltage of the pga is in pga vvo = (3) (3) if 0 > v in > -0.7 v and the pga operates in invert er mode, the output voltage of the pga is in pga vrr vo ?= )/( 12 (4) note: if v in is negative, it should not be lower than - 0.7v to avoid leakage current.
rev. 1.20 112 january 3, 2017 rev. 1.20 113 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu offset calibration the ocp circuit has 4 operating mode controlled by ocpm1~ocpm0 . one of these modes is the calibration mode. in the calibration mode, the op and comparator offset can be calibrated. opamp calibration: ? step1: set ocpm[1:0] =11, ocpaofm=1, the ocp is now in the opamp calibration mode. ? step2: set ocpaof4~ocpaof0 =00000 then read the ocpax bit status . ? step3: let ocpaof=ocpaof+1 then read the ocpax bit status ; if ocpax is changed , record the register data as vos1 . ? step4: set ocpaof [4:0] 111111 then read the ocpax bit status . ? step5: let ocpaof=ocpaof-1 then read the ocpax bit status ; if ocpax is changed , record the register data as vos2 . ? step6: restore vos = (vos1 + vos2)/2 to the ocpaof register . t he calibration is now fnished. comparator calibration: ? step1: set ocpm[1:0] =11, ocpcofm=1, the ocp is now in the comparator calibration mode ? step2: set ocpcof [4:0] =00000 then read the ocpcx bit status. ? step3: let ocpcof=ocpcof+1 then read the ocpcx bit status ; if ocpcx is changed , record the register data as vos1 . ? step4: set ocpcof [4:0] =11111 then read the ocpcx bit status . ? step5: let ocpcof=ocpcof-1 then read the ocpcx bit status ; if ocpcx data is changed , record the register data as vos2. ? step6: restore vos = (vos1 + vos2)/2 to the ocpcof register . the calibration is now fnished. ocp register description the ocp0 and ocp1 registers are the ocp control registers which control the ocp operation mode, pga a nd fl ter f unctions. t he oc pref r egister i s u sed t o p rovide t he r eference v oltages f or t he o ver current protection. ocp acal and ocpccal are used to cancel out the operational amplifer and comparator input offset. ocpc0 register bit 7 6 5 4 3 2 1 0 name ocpm1 ocpm0 r/w r/w r/w por 0 0 bit 7~6 ocpm1~ocpm0: mode selection 00: ocp function disable, s1, s3 on , s0,s2 off 01: ocp function enable in non-inverter mode, s0, s3 on , s1,s2 off 10: ocp function enable in inverter mode , s1, s2 on , s0,s3 off 11: ocp function enable in 0v input mode, s1, s3 on , s0,s2 off note: disable means opa, cmp, dac, filter all off & comparato r output=low. bit 5~0 unimplemented, read as 0
rev. 1.20 114 january 3, 2017 rev. 1.20 115 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ocpc1 register bit 7 6 5 4 3 2 1 0 name ocpo ocpg2 ocpg1 ocpg0 ocpflt2 ocpflt1 ocpflt0 r/w r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 ocp o : ocpo output (read only) bit 6 unimplemented reead as 0 bit 5~3 ocpg2~ocpg0: opa gain i nverter mode: 000: -1 001: -5 010: -10 011: -15 100: -20 101: -30 110: -40 111: -50 non-inverter mode: 000: 1 001: 6 010: 1 1 011: 1 6 100: 2 1 101: 3 1 110: 4 1 111: 5 1 bit 2~0 ocpflt2~ocpflt0: demodula tor filter selection 000: 0 t flt ( without flter) 001: 1~2 t flt 010: 3~4 t flt 011: 7~8 t flt 100: 15~16 t flt 101: 31~32 t flt 110: 63~64 t flt 111: 127~128 t flt note: f flt = f h /4, f h =f hxt (crystal) , t flt =1/f flt ocpref register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 5~0 ocpref: select reference voltage for over current protect reference voltage= (dac reference voltage /256) (n) , n=ocpr ef[7:0]
rev. 1.20 114 january 3, 2017 rev. 1.20 115 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ocpacal register C over current opa calibration register bit 7 6 5 4 3 2 1 0 name ocpaofm ocpars ocpaof5 ocpaof4 ocpaof3 ocpaof2 ocpaof1 ocpaof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit7 ocpaofm: input offset voltage cancellation mode or normal operating mode selection 0: normal operating mode 1: input offset voltage cancellation mode bit6 ocpars: input offset voltage cancellation reference selection bit 0: select negative input as the reference input 1: select positive input as the reference input bit 5~0 ocp aof4~ocpaof0 : input offset voltage calibration control ocpccal register C over current comparator calibration register bit 7 6 5 4 3 2 1 0 name ocp axcx ocpcofm ocpcrs ocpcof4 ocpcof3 ocpcof2 ocpcof1 ocpcof0 r/w r r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit7 ocp axcx: opa/ comparator output for calibration; positive logic (read only) i f ocpaofm=1, this bit is the opa output for calibration i f ocpcofm=1, this bit is the comparator output for calibration note: ocpaofm and ocpcofm can t be 1 simultaneously. bit6 ocpcofm: input offset voltage cancellation mode or normal operating mode selection 0: normal operating mode 1: input offset voltage cancellation mode bit5 ocpcrs: input offset voltage cancellation reference selection bit 0: select negative input as the reference input 1: select positive input as the reference input bit 4~0 ocpcof4~ocpcof0 : input offset voltage calibration control dcmisc register bit 7 6 5 4 3 2 1 0 name demdavr ocdavr demo ais1 ais0 r/w r/w r/w r r/w r/w por 0 0 0 0 0 bit 7 demdavr : demodulation dac vref source 0: a vdd 1: internal vref bit 6 ocdavr : ocp dac vref source 0: a vdd 1: internal vref bit 5 demo : demodulation output(read only) bit 1~0 ais1~ais0: demodulation opa input selection 00: comm0 01: comm1 10: comm2 11: comm2
rev. 1.20 116 january 3, 2017 rev. 1.20 117 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu internal reference voltage C ivref r1 r2 a g=2 band gap ivref to adc v ref to adc input v bg internal reference voltage circuit the bandgap circuit will automatically switch on if either the lvr or lvd is enabled or if the vref is enabled. demodulator & ocp miscellaneous control register description t he dcmisc r egister i s u sed t o c ontrol t he d/ a vre f sou rce se lection, t o st ore t he o perational amplifer output status as a logical condition and to select the demodulat or op a input source . the vrefc register is used to control vref and to store the vref op a output status. vracal is the vref opa calibration register. vrefc register bit 7 6 5 4 3 2 1 0 name vrefen vrax r/w r/w r por 0 0 bit 7 vrefen: vref enable bit 0: disable 1: enable note: the bandgap will be enabled if either the lvr , lvd , vbg (adc) or vref is enable d . bit 0 vrax: vref opa output, read only. vracal register C vref opa calibration register bit 7 6 5 4 3 2 1 0 name vraofm vrars vraof5 vraof4 vraof3 vraof2 vraof1 vraof0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 0 0 0 0 0 bit7 vraofm: input offset voltage cancellation mode or normal operating mode selection 0: normal operating mode 1: input offset voltage cancellation mode bit6 vrars: input offset voltage cancellation reference selection bit 0: select negative input as the reference input 1: select positive input as the reference input bit 5~0 vraof5~vraof0: comparator input offset voltage calibration control
rev. 1.20 116 january 3, 2017 rev. 1.20 117 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu interrupts interrupts are an important part of any microcontroller s ystem. when an external event or an internal function such as a t imer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupt is generated by the action of the external int1 pins, while the internal interrupts are generated by various internal functions such as the tms, demodulation, ocp, t ime base, lvd, eeprom and the a/d converter. interrupt registers overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the special purpose data memory , as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. t he frst i s t he int c0~intc2 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the mfi0~mfi2 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each regist er contai ns a number of enable bit s to enable or disa ble indivi dual regist ers as wel l as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global emi intn pin intne intnf n=1 ocp ocpe ocpf demodulation deme demf a/d converter ade adf multi-function mfne mfnf n=0~2 time base tbne tbnf n=0 or 1 i 2 c iice iicf lvd lve lvf eeprom dee def tm tnpe tnpf n=0 or 1 tnae tnaf interrupt register bit naming conventions interrupt register contents name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 integ int1s1 int1s0 pwms1 pwms0 intc0 pwmsf demf ocpf pwmse deme ocpe emi intc1 adf mf2f mf1f mf0f ade mf2e mf1e mf0e intc2 int1f tb1f tb0f iicf int1e tb1e tb0e iice mfi0 t0af t0pf t0ae t0pe mfi1 t1af t1pf t1ae t1pe mfi2 def lvf dee lve
rev. 1.20 118 january 3, 2017 rev. 1.20 119 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu integ register bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 pwms1 pwms0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as "0" bit 3 ~ 2 int1s1, int1s0: defnes int1 interrupt active edge 00: disabled interrupt 01: rising edge interrupt 10: falling edge interrupt 11: dual edge interrupt bit 1 ~ 0 pwms1, pwms0: defnes pwm synchronization signal interrupt active edge 00: disabled interrupt 01: rising edge interrupt 10: falling edge interrupt (must be fxed at this setting) 11: dual edge interrupt note: the pwms[1:0] feld must be fxed at "10" if the pwms interrupt is required. when this bit feld is equal to "01" or "11", the function will not be garanteed. intc0 register bit 7 6 5 4 3 2 1 0 name pwmsf demf ocpf pwmse deme ocpe emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 pwmsf: pwm synchronization signal interrupt request flag 0: no request 1: interrupt request bit 5 demf: demodulation interrupt request fag 0: no request 1: interrupt request bit 4 ocpf: over current protection interrupt request fag 0: no request 1: interrupt request bit 3 pwmse: pwm synchronization signal interrupt control 0: disable 1: enable bit 2 deme: demodulation interrupt control 0: disable 1: enable bit 1 ocpe: over current protection interrupt control 0: disable 1: enable bit 0 emi: global interrupt control 0: disable 1: enable
rev. 1.20 118 january 3, 2017 rev. 1.20 119 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu intc1 register bit 7 6 5 4 3 2 1 0 name adf mf2f mf1f mf0f ade mf2e mf1e mf0e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 6 mf2f: multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 5 mf1f: multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 4 mf0f: multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 3 ade : a/d converter interrupt control 0: disable 1: enable bit 2 mf2e: multi-function interrupt 2 control 0: disable 1: enable bit 1 mf1e: multi-function interrupt 1 control 0: disable 1: enable bit 0 mf0e: multi-function interrupt 0 control 0: disable 1: enable intc2 register bit 7 6 5 4 3 2 1 0 name int1f tb1f tb0f iicf int1e tb1e tb0e iice r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 int1f: int1 interrupt request flag 0: no request 1: interrupt request bit 6 tb1f: t ime base 1 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f: t ime base 0 interrupt request flag 0: no request 1: interrupt request bit 4 iicf: i 2 c interrupt request flag 0: no request 1: interrupt request bit 3 int1e: int1 interrupt control 0: disable 1: enable bit 2 tb1e: t ime base 1 interrupt control 0: disable 1: enable bit 1 tb0e: t ime base 0 interrupt control 0: disable 1: enable bit 0 iice: i 2 c interrupt control 0: disable 1: enable
rev. 1.20 120 january 3, 2017 rev. 1.20 121 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu mfi0 register bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 t0af: tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf: tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 ~ 2 unimplemented, read as "0" bit 1 t0ae: tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe: tm0 comparator p match interrupt control 0: disable 1: enable mfi1 register bit 7 6 5 4 3 2 1 0 name t1af t1pf t1ae t1pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 t1af: tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf: tm1 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 ~ 2 unimplemented, read as "0" bit 1 t1ae: tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe: tm1 comparator p match interrupt control 0: disable 1: enable
rev. 1.20 120 january 3, 2017 rev. 1.20 121 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu mfi2 register bit 7 6 5 4 3 2 1 0 name def lvf dee lve r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 def: data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf: lvd interrupt request fag 0: no request 1: interrupt request bit 3 ~ 2 unimplemented, read as "0" bit 1 dee: data eeprom interrupt control 0: disable 1: enable bit 0 lve: lvd interrupt control 0: disable 1: enable interrupt operation when the conditions for an interrupt event occur , such as a tm comparator p or comparator a match or a/ d conversion completion etc, the relevant interrupt request fag wi ll be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter , which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti, whi ch re trieves t he ori ginal progra m count er a ddress from t he st ack a nd a llows t he microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . o nce an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. al l o f t he i nterrupt r equest fa gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n sl eep o r idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode.
rev. 1.20 122 january 3, 2017 rev. 1.20 123 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu demodulation ocpf demf ocpe deme 04h 08h pwms pwmsf pwmse 0ch interrupt name request flags enable bits master enable vector emi auto disabled in isr low interrupts contained within multi-function interrupts priority high xxe enable bits xxf request flag , auto reset in isr legend xxf request flag , no auto reset in isr 28h tb1f tb1e time base 1 i 2 c iicf iice 20h in1t int1f int1e 24h tb0f tb0e time base 0 14h multi-function 1 mf1f mf1e 1ch a/d adf ade ocp emi emi emi emi emi emi emi emi 2ch emi 18h multi-function 2 mf2f mf2e emi 10h multi-function 0 mf0f mf0e emi tm0 a t0af t0ae tm0 p t0pf t0pe tm1 a t1af t1ae tm1 p t1pf t1pe lvd lvf lve eeprom def dee interrupt name request flags enable bits interrupt structure external interrupt the e xternal i nterrupts a re c ontrolled b y si gnal t ransitions o n t he p in int 1. an e xternal i nterrupt request will take place when the external interrupt request fag, int1f , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int1e, must frst be set. additionally the correc t i nterrupt edge t ype must be se lected usi ng t he int eg regi ster t o ena ble t he ext ernal interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be confgured as external interrupt pins if their external interrupt enable bit i n t he c orresponding i nterrupt r egister h as b een se t. t he p in m ust a lso b e se tup a s a n i nput b y setting t he c orresponding bi t i n t he port c ontrol re gister. w hen t he i nterrupt i s e nabled, t he st ack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. when the interrupt is serviced, the external interrupt request fag, int1f , will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will rema in valid even if the pin is used as an external interrupt input. the integ register is used to se lect t he t ype of a ctive e dge t hat wi ll t rigger t he e xternal i nterrupt. a c hoice of e ither ri sing or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function.
rev. 1.20 122 january 3, 2017 rev. 1.20 123 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu multi-function interrupt within this device there are up to three multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, lvd interrupt and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf2f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request fag. t o allow the program to branch to its respective interrupt vector address, when the multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi- function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. however, i t m ust be not ed t hat, a lthough t he mul ti-function int errupt fa gs wi ll be a utomatically reset when the interrupt is serviced, the request flags from the original source of the multi- function interrupts, namely the tm interrupts, l vd interrupt and eeprom interrupt will not be automatically reset and must be manually reset by the application program. ocp interrupt the oc p i nterrupt i s c ontrolled b y d etecting a h uge c urrent. an oc p i nterrupt r equest wi ll t ake place when the ocp interrupt request flag, ocpf , is set, which occurs when a huge current is detected. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and ocp interrupt enable bit, ocpe, must frst be set. when the interrupt is enabled , the stack is not full and a huge current is detected, a subroutine call to the ocp interrupt vector, will take place. when the interrupt is serviced, the ocp interrupt flag, ocpf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. demodulation interrupt the demodulation interrupt is controlled by the demodulation process. a demodulation interrupt request w ill take place w hen the d emodulation interrupt reques t f ag, d emf, is s et, w hich occurs when the demodulation process fnishes. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and demodulation interrupt enable bit, deme, must frst be set. when the interrup t is enabled, the stack is not full and demodulation process has ended, a subroutine call to the demodulation interrupt vector , will take place. when the interrupt is serviced, the demodulation interrupt fag, demf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/ d converter interrupt request will take place when the a/d converter interrupt request fag, adf , is set, which occurs when the a/d conversion process fnishes. t o allow the program to branch to its respective interrupt vector a ddress, the global interrupt enable bit, emi, a nd a/ d interrupt enable bit, ade, must frst be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector , will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf , will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts.
rev. 1.20 124 january 3, 2017 rev. 1.20 125 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu time base interrupts the function of the t ime base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request flags, tb0f or tb1f will be set. t o allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and t ime base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the t ime base overfow s, a subroutine call to their res pective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f , will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the t ime base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a prescaler, the prescaltion ratio of which is selected by programming the appropriate bits in the pscr register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the t ime base interrupt period, can originate from f sys , f sys /4 or f sub by setting c lksel1~cl ksel0 bits in the pscr register. tbc0 register bit 7 6 5 4 3 2 1 0 name tb0en tb02 tb01 tb00 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb0en: tb0 control bit 0: disable 1: enable bit 6~3 unimplemented, read as "0" bit 2 ~ 0 tb02 ~ tb00: select t ime base 0 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb tbc1 register bit 7 6 5 4 3 2 1 0 name tb1en tb12 tb11 tb10 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 tb1en: tb1 control bit 0: disable 1: enable bit 6~3 unimplemented, read as "0" bit 2 ~ 0 tb12 ~ tb10: select t ime base 1 t ime-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb
rev. 1.20 124 january 3, 2017 rev. 1.20 125 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu pscr register bit 7 6 5 4 3 2 1 0 name clksel1 clksel0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1 ~ 0 c lksel1 ~ clksel0: f tb clock source selection 00: f sys 01: f sys /4 11: f sub

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time base interrupt eeprom interrupt the eeprom interrupt is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request flag, def , is set, which occurs when an eeprom w rite cycl e ends. t o allow the program to branch to its respective interrupt vector a ddress, t he gl obal i nterrupt e nable bi t, e mi, a nd e eprom int errupt e nable bi t, de e, and ass ociated multi-function interrupt enable bit, mf2e, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom w rite cycle ends, a subroutine call to the respective eeprom interrupt vector , will take place. when the eeprom interrupt is serviced, the emi bit will be automatica lly cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the l ow v oltage de tector i nterrupt i s c ontained wi thin t he mu lti-function i nterrupt. an l vd interrupt reques t w ill take place w hen the l vd interrupt request flag, l vf, is s et, w hich occurs when the low v oltage detector function detects a low power supply voltage. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and low voltage interrupt enable bit, l ve, and associated multi-function interrupt enable bit, mf2e, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the l vd interrupt vector , will take place. when the low v oltage interrupt is serviced, t he e mi bi t wi ll be a utomatically c leared t o di sable ot her i nterrupts, ho wever on ly t he multi-function interrupt request fag will be also automatically cleared . as the l vf fag will not be automatically cleared, it has to be cleared by the application program.
rev. 1.20 126 january 3, 2017 rev. 1.20 127 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu tm interrupts the standard t ype tm and compact t ype tm have two interrupts each. all of the tm interrupts are conta ined within the multi-func tion interrupts. for each of the standard and compact t ype tm there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p or comparator a match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the respective tm interrupt enable bit, and associated multi-function interrupt enable bit, mfnf (mf0f or mf1f), must frst be set. when the int errupt is enabled, the stack is not full and a tm comparator match situati on occurs, a subroutine call to the relevant tm interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to dis able other interrupts , however only the related m fnf fag (m f0f or m f1f) w ill be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. i 2 c interrupt a n i 2 c interrupt request will take place when the i 2 c interrupt request flag, iicf , is set, which occurs when a byte of data has been received or transmitted by the i 2 c interface. t o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the se rial int erface int errupt e nable bi t, iice , m ust frst be se t. w hen t he i nterrupt i s e nabled, t he stack is not full and a byte of data has been transmitted or received by the i 2 c interface, a subroutine call to the respective interrupt vect or, will take place. when the i 2 c interface interrupt is serviced, the interrupt request fag, iicf , will be automatically reset and the emi bit will be cleared to disable other interrupts. interrupt wake-up function each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function.
rev. 1.20 126 january 3, 2017 rev. 1.20 127 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu programming considerations by di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained w ithin a m ulti-function interrupt, then w hen the interrupt service routine is executed, as only the m ulti-function interrupt reques t f ags, m f0f~mf2f, w ill be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately . if only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every i nterrupt h as t he c apability o f wa king u p t he m icrocontroller wh en i t i s i n sl eep o r i dle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts.
rev. 1.20 128 january 3, 2017 rev. 1.20 129 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu low voltage detector C lvd the device has a low v oltage detector function, also know n as l vd. this enables the device to monitor the power supply voltage, v dd , and provides a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low v oltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name l vdc. three bits in this register , vl vd2~vlvd0, are used to select one of eight fxed voltages below which a l ow vo ltage c ondition wi ll be de te r mined. a l ow vo ltage c ondition i s i ndicated whe n t he l vdo bit is set. if the l vdo bit is low , this indicates that the v dd voltage is above the preset low voltage value. the l vden bit is used to control the overall on/of f function of the low voltage detector . setting the bit high will enable the low voltage detector . clearing the bit to zero will switch of f the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd2 vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 lvdo: lvd output flag 0: no low v oltage detect 1: low v oltage detect bit 4 lvden: low v oltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vl vd2 ~ vlvd0: select lvd v oltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.0v
rev. 1.20 128 january 3, 2017 rev. 1.20 129 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu lvd operation the low v oltage detector function operates by comparing the pow er supply voltage, v dd , with a pre-specifed volta ge level stored in the l vdc register . this has a range of between 2.0v and 4.0v . when the power supply voltage, v dd , falls below this pre-determined value, the l vdo bit will be set high indicating a low power supply voltage condition. the low v oltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the l vden bit is high. after enabling the low voltage detector , a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly , at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low v oltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the l vdo bit. the interrupt will only be generated after a delay of t lvd after the l vdo bit has been set high by a low voltage condition. when the device is powered down the low v oltage detector will rema in active if the l vden bit is high. in this case, the l vf interrupt request fag will be set, causing an interru pt to be generated if vdd falls below the preset l vd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low v oltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode.
rev. 1.20 130 january 3, 2017 rev. 1.20 131 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu application circuits wpc type a11 transmitter
rev. 1.20 130 january 3, 2017 rev. 1.20 131 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu
rev. 1.20 132 january 3, 2017 rev. 1.20 133 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu bill of materials p a r t n a m e d e s i g n a t o r b r a n d p a r t n u m b e r p a c k a g e t y p e q u a n t i t y mcu u6 holtek HT66FW2230 ssop28 1 opa u7 holtek ht9252 sop8 1 gate driver u8, u9 ti ti tps28225 sop8 2 opa u10 ti ti ina199 sc70 1 n-mosfet u1, u2 advance power ap4226gm sop8 2 inductor u3, u4 gotrend gw505006pt-08b10rtn 1 usb_micro u5 fci #10103592-0001lf (b type) 1 crystal y1 abracon crystal abm8g-20.000mhz-4y-t3 1 capacitor c1, c7, c10, c16, c19, c22, c23, c29, c31, c35, c37 murata / walsin 0.1uf/25v smd 0603 11 capacitor c2, c4, c5, c18, c24, c30, c32, c36 murata / walsin 10uf/10v smd 0805 8 capacitor c3, c6, c8, c9 murata 104/50v, npo, grm31c5c1h104ja01l smd 1206 4 capacitor c11 murata / walsin 5.6nf/25v smd 0603 1 capacitor c12, c15, c26 murata / walsin 4.7nf/10v smd 0603 3 capacitor c13, c25 murata / walsin 10nf/25v smd 0603 2 capacitor c14, c17 murata / walsin 100nf/10v smd 0603 2 capacitor c20 murata / walsin 472/16v smd 0603 1 capacitor c21 murata / walsin 220pf/16v smd 0603 1 capacitor c27 murata / walsin 0.1u/10v smd 0603 1 capacitor c33, c34 murata 0.1uf/50v, x7r 10% smd 0805 2 capacitor c38, c39 murata / walsin 10pf/10v smd 0603 2 diode d1 diodes bav21ws-7-f 250v 200ma sod 323 1 led d2 everlight led (green) smd 0603 1 led d3 everlight led (blue) smd 0603 1 connector j1 -- -- con2 (vdd) 1 connector j2 -- -- con2 (vss) 1 connector j3 -- -- con4 (ocds) 1 buzzer ls1 kingstate kcg0601(buzzer) 1 p-mosfet q1 alpha & omega ao3401, pmos, #85-1001-1-nd sot-23 1 resistor r1, r16, r19, r23, r45 liket 100k smd 0603 5 resistor r4, r5, r7, r8 liket 10 smd 0603 4 resistor r6 liket 47k smd 0603 1 resistor r11, r30, r31, r39 liket 1k smd 0603 4 resistor r12 liket 82k smd 0603 1 resistor r13 liket 1.5k smd 0603 1 resistor r14 liket 6.8k smd 0603 1 resistor r15 liket 33k smd 0603 1 resistor r17, r21, r40, r41 liket 10k smd 0603 4 temp. sensor r18 semitec 10k, ntc #954-103at-4-80025 smd 1210 1 resistor r20 liket 2m smd 0603 1 resistor r22 liket 1k (1%) smd 0603 1 resistor r24, r26, r29 liket reserved smd 0603 3 resistor r25 liket 680k smd 0603 1 resistor r27, r28, r32, r34, r35, r36 liket 0 smd 0603 6 resistor r33 liket 130k smd 0603 1 resistor r37 liket 3k smd 0603 1 resistor r38 liket 20k smd 0603 1 resistor r43, r44 liket 1r smd 0603 2 resistor rse1 ohmite 0.05r, 1w #mcs1632r050fer smd 1210 1 resistor rse2 ohmite 0.02r, 1w #mcs1632r020fer smd 1210 1
rev. 1.20 132 january 3, 2017 rev. 1.20 133 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontroller , a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be i mplemented wi thin 0.5 s a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed.
rev. 1.20 134 january 3, 2017 rev. 1.20 135 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu logical and rotate operation the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application which rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or t o a su broutine usi ng t he cal l i nstruction. t hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. this is done by placing a return ins truction " ret" in the s ubroutine w hich w ill cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is frst made regarding the c ondition of a c ertain da ta m emory or i ndividual bi ts. de pending upon t he c onditions, t he program will continue with the next instruction or skip over it and jump to the following instruction. these i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers . this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is take n care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. however , whe n worki ng wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "hal t" i nstruction f or po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections.
rev. 1.20 134 january 3, 2017 rev. 1.20 135 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] add data memory to acc 1 z, c, ac, ov addm a,[m] add acc to data memory 1 note z, c, ac, ov add a,x add immediate data to acc 1 z, c, ac, ov adc a,[m] add data memory to acc with carry 1 z, c, ac, ov adcm a,[m] add acc to data memory with carry 1 note z, c, ac, ov sub a,x subtract immediate data from the acc 1 z, c, ac, ov sub a,[m] subtract data memory from acc 1 z, c, ac, ov subm a,[m] subtract data memory from acc with result in data memory 1 note z, c, ac, ov sbc a,[m] subtract data memory from acc with carry 1 z, c, ac, ov sbcm a,[m] subtract data memory from acc with carry, result in data memory 1 note z, c, ac, ov daa [m] decimal adjust acc for addition with result in data memory 1 note c logic operation and a,[m] logical and data memory to acc 1 z or a,[m] logical or data memory to acc 1 z xor a,[m] logical xor data memory to acc 1 z andm a,[m] logical and acc to data memory 1 note z orm a,[m] logical or acc to data memory 1 note z xorm a,[m] logical xor acc to data memory 1 note z and a,x logical and immediate data to acc 1 z or a,x logical or immediate data to acc 1 z xor a,x logical xor immediate data to acc 1 z cpl [m] complement data memory 1 note z cpla [m] complement data memory with result in acc 1 z increment & decrement inca [m] increment data memory with result in acc 1 z inc [m] increment data memory 1 note z deca [m] decrement data memory with result in acc 1 z dec [m] decrement data memory 1 note z rotate rra [m] rotate data memory right with result in acc 1 none rr [m] rotate data memory right 1 note none rrca [m] rotate data memory right through carry with result in acc 1 c rrc [m] rotate data memory right through carry 1 note c rla [m] rotate data memory left with result in acc 1 none rl [m] rotate data memory left 1 note none rlca [m] rotate data memory left through carry with result in acc 1 c rlc [m] rotate data memory left through carry 1 note c
rev. 1.20 136 january 3, 2017 rev. 1.20 137 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu mnemonic description cycles flag affected data move mov a,[m] move data memory to acc 1 none mov [m],a move acc to data memory 1 note none mov a,x move immediate data to acc 1 none bit operation clr [m].i clear bit of data memory 1 note none set [m].i set bit of data memory 1 note none branch jmp addr jump unconditionally 2 none sz [m] skip if data memory is zero 1 note none sza [m] skip if data memory is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memory is zero 1 note none snz [m].i skip if bit i of data memory is not zero 1 note none siz [m] skip if increment data memory is zero 1 note none sdz [m] skip if decrement data memory is zero 1 note none siza [m] skip if increment data memory is zero with result in acc 1 note none sdza [m] skip if decrement data memory is zero with result in acc 1 note none call addr subroutine call 2 none ret return from subroutine 2 none ret a,x return from subroutine and load immediate data to acc 2 none reti return from interrupt 2 none table read tabrd [m] read table (specifc page) to tblh and data memory 2 note none tabrdc [m] read table (current page) to tblh and data memory 2 note none tabrdl [m] read table (last page) to tblh and data memory 2 note none miscellaneous nop no operation 1 none clr [m] clear data memory 1 note none set [m] set data memory 1 note none clr wdt clear watchdog timer 1 to, pdf clr wdt1 pre-clear watchdog timer 1 to, pdf clr wdt2 pre-clear watchdog timer 1 to, pdf swap [m] swap nibbles of data memory 1 note none swapa [m] swap nibbles of data memory with result in acc 1 none halt enter power down mode 1 to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. f or the " clr wd t1" and " clr wd t2" ins tructions the t o and p df flags may be af fected by the execution status. the t o and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged.
rev. 1.20 136 january 3, 2017 rev. 1.20 137 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z
rev. 1.20 138 january 3, 2017 rev. 1.20 139 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z
rev. 1.20 138 january 3, 2017 rev. 1.20 139 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z
rev. 1.20 140 january 3, 2017 rev. 1.20 141 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none
rev. 1.20 140 january 3, 2017 rev. 1.20 141 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i=0~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i=0~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 [ m].0 affected f ag(s) none
rev. 1.20 142 january 3, 2017 rev. 1.20 143 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); (i=0~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i=0~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m]=0 affected f ag(s) none
rev. 1.20 142 january 3, 2017 rev. 1.20 143 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc=0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m]=0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc=0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c
rev. 1.20 144 january 3, 2017 rev. 1.20 145 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7~[m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3~acc.0 [ m].7~[m].4 acc.7~acc.4 [ m].3~[m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m]=0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m]=0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip if [ m].i=0 affected f ag(s) none
rev. 1.20 144 january 3, 2017 rev. 1.20 145 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu tabrd [m] read ta ble ( specifc p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( specifc p age) a ddressed b y t he t able p ointer p air (tbhp a nd t blp) i s mo ved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z
rev. 1.20 146 january 3, 2017 rev. 1.20 147 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website for the latest version of the package/carton information . additional supplementary information with regard to pa ckaging is listed below. click on the relevant section to be transferred to the relevant website page. ? package information (include outline dimensions, product t ape and reel specifcations) ? the operation instruction of packing materials ? carton information
rev. 1.20 146 january 3, 2017 rev. 1.20 147 january 3, 2017 HT66FW2230 wireless charger a/d flash mcu 28-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.236 bsc b 0.154 bsc c 0.008 0.012 c 0.390 bsc d 0.069 e 0.025 bsc f 0.004 0.0098 g 0.016 0.050 h 0.004 0.010 0 8 symbol dimensions in mm min. nom. max. a 6.000 bsc b 3.900 bsc c 0.20 0.30 c 9.900 bsc d 1.75 e 0.635 bsc f 0.10 0.25 g 0.41 1.27 h 0.10 0.25 0 8
rev. 1.20 148 january 3, 2017 rev. 1.20 pb january 3, 2017 HT66FW2230 wireless charger a/d flash mcu copyright ? 2017 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifcations described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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